Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein

Claim 2

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activate said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal, wherein said electric circuit means comprises means for supplying said external terminal with said particular electric signal continuously after selecting one of said spare memory cells during writing and reading data.

Claim 3

The semiconductor memory device according to claim 1, wherein said electric circuit means includes: means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal.

Claim 4

The semiconductor memory device according to claim 2, wherein said providing means includes: current generating means responsive to application of a predetermined potential to said predetermined external terminal for generating current which flows between said predetermined external terminal and said providing means; and current increasing means responsive to said signal at the predetermined logic level held by said holding means for increasing said current.

Claim 5

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal, said electric circuit means including means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, said providing means including: current generating means responsive to application of a predetermined potential to said predetermined external terminal for generating current which flows between said predetermined external terminal and said providing means; and current increasing means responsive to said signal at the predetermined logic level held by said holding means for increasing said current; wherein said current generating means includes first electric path forming means responsive to the application of said predetermined potential to said predetermined external terminal for forming a first electric path between said predetermined external terminal and a predetermined potential source, and said current increasing means includes second electric path forming means responsive to said signal at the predetermined logic level held in said holding means and the application of said predetermined potential to said predetermined external terminal for forming a second electric path between said predetermined external terminal and said predetermined potential source.

Claim 6

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal, said electric circuit means including means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, said providing means including: current generating means responsive to application of a predetermined potential to said predetermined external terminal for generating current which flows between said predetermined external terminal and said providing means; and current increasing means responsive to said signal at the predetermined logic level held by said holding means for increasing said current; wherein said current generating means includes first electric path forming means responsive to the application of said predetermined potential to said predetermined external terminal for forming a first electric path between said predetermined external terminal and a predetermined potential source, and said current increasing means includes second electric path forming means responsive to said signal at the predetermined logic level held in said holding means and the application of said predetermined potential to said predetermined external terminal for forming a second electric path between said predetermined external terminal and said predetermined potential source.

Claim 7

The semiconductor memory device according to claim 4, wherein said first electric path forming means includes a first field effect semiconductor element having a first conduction terminal connected to said predetermined external terminal, a second conduction terminal connected to said predetermined potential source, and a control terminal connected to said predetermined potential source.

Claim 8

The semiconductor memory device according to claim 4, wherein said second electric path forming means includes: a second field effect semiconductor element having a first conduction terminal connected to said predetermined external terminal, a second conduction terminal, and a control terminal connected to said second conduction terminal; and a third field effect semiconductor element having a first conduction terminal connected to said second conduction terminal of said second field effect semiconductor element, a second conduction terminal connected to said predetermined potential source, and a control terminal for receiving said signal held in said holding means.

Claim 9

The semiconductor memory device according to claim 5, wherein the polarity of said predetermined potential is negative, the potential of said predetermined potential source is a ground potential, and the polarity of said first field effect semiconductor element is N type.

Claim 10

The semiconductor memory device according to claim 6, wherein the polarity of said predetermined potential is negative, the potential of said predetermined potential source is a ground potential, said predetermined logic level is a high level, and the polarity of each of said second and third field effect semiconductor elements is N type.

Claim 11

The semiconductor memory device according to claim 2, wherein said providing means includes application potential switching means for applying a potential at a first logic level to said predetermined external terminal when a signal held in said holding means is a signal at said predetermined logic level and applying a potential at a second logic level to said predetermined external terminal when said held signal is a signal at another logic level.

Claim 12

The semiconductor memory device according to claim 9, wherein said application potential switching means includes first switching means coupled between a potential at said first logic level and said predetermined external terminal, second switching means coupled between a potential at said second logic level and said predetermined external terminal, and control means responsive to said signal held in said holding means for controlling said first and second switching means.

Claim 13

The semiconductor memory device according to claim 10, wherein said control means is responsive to said signal at the predetermined logic level held in said holding means for turning on said first switching means and turning off said second switching means.

Claim 14

The semiconductor memory device according to claim 11, wherein said control means is activated in response to a predetermined activating signal.

Claim 15

The semiconductor memory device according to claim 12, wherein said control means includes: first logical circuit means for forming a logical product signal of said signal held in said holding means and said predetermined activating signal; inverter means for inverting said signal held in said holding means; and second logical circuit means for forming a logical product signal of said signal inverted by said inverter means and said predetermined activating signal, wherein said first switching means is controlled by said signal formed by said first logical circuit means, and said second switching means is controlled by said signal formed by said second logical circuit means.

Claim 16

The semiconductor memory device according to claim 13, wherein said first switching means includes a first field effect semiconductor element, which has a first conduction terminal for receiving a potential at said first logic level, a second conduction terminal connected to said predetermined external terminal, and a control terminal receiving said signal formed by said first logical circuit means, and said second switching means includes a second field effect semiconductor element, which has a first conduction terminal for receiving a potential at said second logic level, a second conduction terminal connected to said predetermined external terminal, and a control terminal for receiving said signal formed by said second logical circuit means.

Claim 17

The semiconductor memory device according to claim 14, wherein said first logic level is a high level, said second logic level is a low level, said predetermined logic level is the high level, and the polarity of each of said first and second field effect semiconductor element is N type.

Claim 18

The semiconductor memory device according to claim 13, wherein each of said first and second logical circuit means includes a two-input NAND gate and an inverter for inverting an output signal of said NAND gate.

Claim 19

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric current means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal, said electric circuit means including means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal; wherein said holding means includes a first node for receiving an output signal of said control signal providing means, a second node, a third node, control signal detecting means for applying a signal at said predetermined logic level to said second node when the potential of at least one of said first node and said third node has the same level as the level of said control signal, and fixing means responsive to the potential of said second node attaining said predetermined logic level, for fixing the potential of said third node to the same level as the level of said control signal.

Claim 20

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric current means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal, said electric circuit means including means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal; wherein said holding means includes a first node for receiving an output signal of said control signal providing means, a second node, a third node, control signal detecting means for applying a signal at said predetermined logic level to said second node when the potential of at least one of said first node and said third node has the same level as the level of said control signal, and fixing means responsive to the potential of said second node attaining said predetermined logic level, for fixing the potential of said third node to the same level as the level of said control signal.

Claim 21

The semiconductor memory device according to claim 17, wherein said control signal detecting means includes first logical circuit means for forming a logical product signal of the potential of said first node and the potential of said third node, and said fixing means includes second logical circuit means for forming a logical product signal of the potential of said second node and the potential at said predetermined logic level.

Claim 22

The semiconductor memory device according to claim 17, further comprising reset means for resetting the potential of said second node to a logic level opposite to said predetermined logic level when said semiconductor memory device starts to operate.

Claim 23

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said nominal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting one of said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting one of said normal memory cells arranged in any one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; first electric circuit means which is set to provide a first particular electric signal to a first external terminal in response to said first control signal; and second electric circuit means which is set to provide a second particular electric signal to a second external terminal in response to said second control signal.

Claim 24

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said nominal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting one of said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting one of said normal memory cells arranged in any one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; first electric circuit means which is set to provide a first particular electric signal to a first external terminal in response to said first control signal; and second electric circuit means which is set to provide a second particular electric signal to a second external terminal in response to said second control signal.

Claim 25

The semiconductor memory device according to claim 20, wherein said first electric circuit means includes: first holding means responsive to said first control signal for holding a signal at a predetermined logic level; and first providing means responsive to said signal at said predetermined logic level held in said first holding means for providing said first particular electric signal to said first external terminal, and said second electric circuit means includes: second holding means responsive to said second control signal for holding a signal at said predetermined logic level; and second providing means responsive to said signal at said predetermined logic level held in said second holding means for providing said second particular electric signal to said second external terminal.

Claim 26

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said normal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting said normal memory cells arranged in one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to each of said first control signal and said second control signal, wherein said electric circuit means comprises means for supplying said external terminal with said particular electric signal continuously after selecting said first and second spare memory cells during writing and reading data.

Claim 27

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said normal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting said normal memory cells arranged in one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to each of said first control signal and said second control signal, wherein said electric circuit means comprises means for supplying said external terminal with said particular electric signal continuously after selecting said first and second spare memory cells during writing and reading data.

Claim 28

The semiconductor memory device according to claim 22, wherein said electric circuit means includes: first holding means responsive to said first control signal for holding a signal at a predetermined logic level; second holding means responsive to said second control signal for holding said signal at said predetermined logic level; detecting means for detecting that at least one of a signal held in said first holding means and signal held in said second holding means is a signal at said predetermined logic level; and providing means responsive to a detected output of said detecting means for providing said particular electric signal to said predetermined external terminal.

Claim 31

The semiconductor memory device according to claim 20, wherein said first and second electric circuit means comprises means for supplying said first and second external terminals with said first and second particular electric signals continuously after selecting said first and second spare memory cells during writing and reading data.

Claim 32

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal; wherein said electric circuit means includes: means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, and said providing means includes: current generating means responsive to application of a predetermined potential to said predetermined external terminal for generating current which flows between said predetermined external terminal and said providing means; and current increasing means responsive to said signal at the predetermined logic level held by said holding means for increasing said current.

Claim 33

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal; wherein said electric circuit means includes: means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, and said providing means includes: current generating means responsive to application of a predetermined potential to said predetermined external terminal for generating current which flows between said predetermined external terminal and said providing means; and current increasing means responsive to said signal at the predetermined logic level held by said holding means for increasing said current.

Claim 34

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal; wherein said electric circuit means includes: means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, said providing means includes application potential switching means for applying a potential at a first logic level to said predetermined external terminal when a signal held in said holding means is a signal at said predetermined logic level and applying a potential at a second logic level to said predetermined external terminal when said held signal is a signal at another logic level, said application potential switching means includes first switching means coupled between a potential at said first logic level and said predetermined external terminal, second switching means coupled between a potential at said second logic level and said predetermined external terminal, and control means responsive to said signal held in said holding means for controlling said first and second switching means, said control means is responsive to said signal at the predetermined logic level held in said holding means for turning on said first switching means and turning off said second switching means, said control means is activated in response to a predetermined activating signal, and includes: first logical circuit means for forming a logical product signal of said signal held in said holding means and said predetermined activating signal; inverter means for inverting said signal held in said holding means; and second logical circuit means for forming a logical product signal of said signal inverted by said inverter means and said predetermined activating signal, wherein said first switching means is controlled by said signal formed by said first logical circuit means, and said second switching means is controlled by said signal formed by said second logic circuit means.

Claim 35

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells; a spare memory cell array having spare memory cells each being capable of replacing any one of said plurality of normal memory cells; normal selection means for selecting any one of said plurality of normal memory cells for writing and reading data; spare selection means for selecting one of said spare memory cells in place of any one of said plurality of normal memory cells; control signal providing means for providing a control signal which activates said spare selection means and deactivates said normal selection means to use said spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to said control signal; wherein said electric circuit means includes: means responsive to said control signal for holding a signal at a predetermined logic level; and means responsive to said signal at the predetermined logic level held by said holding means for providing said particular electric signal to said predetermined external terminal, said providing means includes application potential switching means for applying a potential at a first logic level to said predetermined external terminal when a signal held in said holding means is a signal at said predetermined logic level and applying a potential at a second logic level to said predetermined external terminal when said held signal is a signal at another logic level, said application potential switching means includes first switching means coupled between a potential at said first logic level and said predetermined external terminal, second switching means coupled between a potential at said second logic level and said predetermined external terminal, and control means responsive to said signal held in said holding means for controlling said first and second switching means, said control means is responsive to said signal at the predetermined logic level held in said holding means for turning on said first switching means and turning off said second switching means, said control means is activated in response to a predetermined activating signal, and includes: first logical circuit means for forming a logical product signal of said signal held in said holding means and said predetermined activating signal; inverter means for inverting said signal held in said holding means; and second logical circuit means for forming a logical product signal of said signal inverted by said inverter means and said predetermined activating signal, wherein said first switching means is controlled by said signal formed by said first logical circuit means, and said second switching means is controlled by said signal formed by said second logic circuit means.

Claim 36

The semiconductor memory device according to claim 27, wherein said first switching means includes a first field effect semiconductor element, which has a first conduction terminal for receiving a potential at said first logic level, a second conduction terminal connected to said predetermined external terminal, and a control terminal receiving said signal formed by said first logical circuit means, and said second switching means includes a second field effect semiconductor element, which has a first conduction terminal for receiving a potential at said second logic level, a second conduction terminal connected to said predetermined external terminal, and a control terminal for receiving said signal formed by said second logical circuit means.

Claim 37

The semiconductor memory device according to claim 28, wherein said first logic level is a high level, said second logic level is a low level, said predetermined logic level is the high level, and the polarity of each of said first and second field effect semiconductor element is N type.

Claim 38

The semiconductor memory device according to claim 27, wherein each of said first and second logical circuit means includes a two-input NAND gate and an inverter for inverting an output signal of said NAND gate.

Claim 39

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said normal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting said normal memory cells arranged in one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to each of said first control signal and said second control signal, wherein said electric circuit means includes: first holding means responsive to said first control signal for holding a signal at a predetermined logic level; second holding means responsive to said second control signal for holding said signal at said predetermined logic level; detecting means for detecting that at least one of a signal held in said first holding means and signal held in said second holding means is a signal at said predetermined logic level; and providing means responsive to a detected output of said detecting means for providing said particular electric signal to said predetermined external terminal.

Claim 40

A semiconductor memory device, comprising: a normal memory cell array having a plurality of normal memory cells arranged in a plurality of rows and a plurality of columns; a first spare memory cell array having first spare memory cells capable of replacing said memory cells arranged in any one of said plurality of rows; a second spare memory cell array having second spare memory cells capable of replacing said normal memory cells arranged in any one of said plurality of columns; first normal selection means for selecting said normal memory cells arranged in any one of said plurality of rows for writing and reading data; second normal selection means for selecting said normal memory cells arranged in one of said plurality of columns for writing and reading data; first spare selection means for selecting one of said first spare memory cells in place of one of said plurality of normal memory cells; second spare selection means for selecting one of said second spare memory cells in place of one of said plurality of normal memory cells; first control signal providing means for providing a first control signal which activates said first spare selection means and deactivates said first normal selection means to use said first spare memory cell array; second control signal providing means for providing a second control signal which activates said second spare selection means and deactivates said second normal selection means to use said second spare memory cell array; and electric circuit means which is set to provide a particular electric signal to a predetermined external terminal in response to each of said first control signal and said second control signal, wherein said electric circuit means includes: first holding means responsive to said first control signal for holding a signal at a predetermined logic level; second holding means responsive to said second control signal for holding said signal at said predetermined logic level; detecting means for detecting that at least one of a signal held in said first holding means and signal held in said second holding means is a signal at said predetermined logic level; and providing means responsive to a detected output of said detecting means for providing said particular electric signal to said predetermined external terminal.