EP0343344A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with improved indicator of the state of the redundant structure
Assignee: NEC Corp
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Filing: 1989-03-28
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Granted: —
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Expires: 2009-03-28
Abstract
Abstract A semiconductor memory device having a redundant cell array and provided with an improved indicating circuit of the selection state of the redundant cell array is disclosed. The memory device comprises a tri-state type output circuit for generating read-out data from the selected memory cell at an output terminal, a detection circuit for generating a detection signal when the memory cell of the redundant cell array is selected and a control circuit for disenabling the output circuit thereby to make the output terminal at a high impedance state in response to the detection signal.
Inventors
- 👤 Tadahiko Sugibayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 19:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
120 words
A semiconductor memory device comprising a normal array of normal memory cells, a redundant array of redundant memory cells, a selection circuit coupled to said normal array and said redundant array for operatively selecting one of said normal memory cells and said redundant memory cells in response to address data, an output terminal, an output circuit coupled to said selection circuit and said output terminal for operatively outputting data from the selected memory cell at said output terminal, a detection circuit coupled to said selection circuit and said output circuit for operatively disenabling said output circuit thereby to set said output terminal at a high impedance state when one of said redundant memory cells is selected by said address data.
Claim 2
Dependent Claim
120 words
A semiconductor memory device comprising a normal array of normal memory cells, a redundant array of redundant memory cells, a selection circuit coupled to said normal array and said redundant array for operatively selecting one of said normal memory cells and said redundant memory cells in response to address data, an output terminal, an output circuit coupled to said selection circuit and said output terminal for operatively outputting data from the selected memory cell at said output terminal, a detection circuit coupled to said selection circuit and said output circuit for operatively disenabling said output circuit thereby to set said output terminal at a high impedance state when one of said redundant memory cells is selected by said address data.
Claim 3
Dependent Claim
45 words
The semiconductor memory device according to claim 1, in which said normal memory cells are arranged in a matrix form of rows and columns in said normal array and said redundant memory cells are arranged in parallel with at least one of row and column.
Claim 4
Dependent Claim
33 words
The semiconductor memory device according to claim 1, further comprising a control terminal for receiving a control signal, and means for enabling said detection circuit when said control signal assumes a predetermined level.
Claim 5
Dependent Claim
149 words
A semiconductor memory device comprising a normal array of memory cells arranged in a matrix form of rows and columns, a redundant array of memory cells arranged in row and columns, a row selection circuit coupled to said normal array and said redundant array for selecting one of the rows of said normal array and said redundant array, a column selection circuit coupled to said normal array and said redundant array for selecting one of the columns of said normal array and said redundant array, an output terminal, an output circuit coupled to said column selection circuit for operatively outputting data derived from the selected column to said output terminal, and a detection circuit coupled to said row selection circuit and said output circuit for disenabling said output circuit thereby to make said output terminal at a high impedance state when the row of said redundant array is selected.
Claim 6
Dependent Claim
149 words
A semiconductor memory device comprising a normal array of memory cells arranged in a matrix form of rows and columns, a redundant array of memory cells arranged in row and columns, a row selection circuit coupled to said normal array and said redundant array for selecting one of the rows of said normal array and said redundant array, a column selection circuit coupled to said normal array and said redundant array for selecting one of the columns of said normal array and said redundant array, an output terminal, an output circuit coupled to said column selection circuit for operatively outputting data derived from the selected column to said output terminal, and a detection circuit coupled to said row selection circuit and said output circuit for disenabling said output circuit thereby to make said output terminal at a high impedance state when the row of said redundant array is selected.
References Cited (Backward Citations)
No citation records indexed.
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