EP0241203A2
Expired / Lapsed
EP
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Detecting repaired memory devices
Assignee: Advanced Micro Devices Inc
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Filing: 1987-03-31
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Granted: —
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Expires: 2007-03-31
Abstract
Abstract A method for detecting repaired memory devices having both primary memory rows and redundant memory rows including the steps of applying a sequence of row addresses to the memory device and detecting whether a primary row has been replaced by a redundant row at one or more of the row addresses. A repair detection circuit is also disclosed which includes a detection comparator coupled, in parallel, to the redundant rows of the memory device, and an enabling comparator responsive to an enabling signal and operative to enable or disable the detection comparator. An further method for memory devices having both redundant rows and redundant columns includes detecting whether either a redundant row or a redundant column of memory cells has been activated by a row or column address.
Inventors
- 👤 Thomas S.W. Wong
- 👤 Thomas Szeto
- 👤 Yuan Mou Su
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 01:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
81 words
A method for detecting repaired memory devices of the type including a plurality of primary memory cells and a plurality of redundant memory cells, where said primary memory cells and said redundant memory cells may be individually addressed, and where a damaged primary memory cell may be replaced by an operational redundant memory cell, said method comprising: applying a sequence of addresses to a memory device; and detecting whether a primary memory cell has been replaced by a redundant memory cell.
Claim 2
Independent Claim
81 words
A method for detecting repaired memory devices of the type including a plurality of primary memory cells and a plurality of redundant memory cells, where said primary memory cells and said redundant memory cells may be individually addressed, and where a damaged primary memory cell may be replaced by an operational redundant memory cell, said method comprising: applying a sequence of addresses to a memory device; and detecting whether a primary memory cell has been replaced by a redundant memory cell.
Claim 3
Dependent Claim
41 words
A method as recited in claim 1 wherein detecting whether a primary memory cell has been replaced by a redundant memory cell includes detecting whether a redundant memory cell is activated by at least one address of said sequence of addresses.
Claim 4
Dependent Claim
30 words
A method as recited in claim 2 further comprising the step of disabling data outputs of said memory cells prior to applying said sequence of addresses to said memory device.
Claim 5
Dependent Claim
43 words
A method as recited in claim 1 wherein at least some of said redundant memory cells are arranged into redundant rows, and wherein applying said sequence of addresses to said memory device comprises applying a sequence of row addresses to said memory device.
Claim 6
Dependent Claim
43 words
A method as recited in claim 4 wherein at least some of said redundant memory cells are arranged into redundant columns, and wherein applying said sequence of addresses to said memory device comprises applying a sequence of column addresses to said memory device.
Claim 7
Dependent Claim
43 words
A method as recited in claim 1 wherein at least some of said redundant memory cells are arranged into redundant columns, and wherein applying said sequence of addresses to said memory device comprises applying a sequence of column addresses to said memory device.
Claim 8
Independent Claim
76 words
A method for detecting repaired memory devices of the type including a first plurality of primary rows of memory cells and a second plurality of redundant rows of memory cells, where a damaged primary row may be replaced by a redundant row, said method comprising: applying a sequence of row addresses to a memory device; and detecting whether a primary row has been replaced by a redundant row at one or more of said row addresses.
Claim 9
Independent Claim
76 words
A method for detecting repaired memory devices of the type including a first plurality of primary rows of memory cells and a second plurality of redundant rows of memory cells, where a damaged primary row may be replaced by a redundant row, said method comprising: applying a sequence of row addresses to a memory device; and detecting whether a primary row has been replaced by a redundant row at one or more of said row addresses.
Claim 10
Dependent Claim
32 words
A method as recited in claim 7 wherein detecting whether a primary row has been replaced by a redundant row includes detecting whether a redundant row is activated by a row address.
Claim 11
Dependent Claim
28 words
A method as recited in claim 8 further comprising disabling data outputs of said memory cells prior to applying said sequence of row addresses to said memory device.
Claim 12
Independent Claim
76 words
A method for detecting repaired memory devices of the type including a first plurality of primary columns of memory cells and a second plurality of redundant columns of memory cells; where a damaged primary column may be replaced by a redundant column, said method comprising: applying a sequence of column addresses to a memory device; and detecting whether a primary column has been replaced by a redundant column at one or more of said column addresses.
Claim 13
Independent Claim
76 words
A method for detecting repaired memory devices of the type including a first plurality of primary columns of memory cells and a second plurality of redundant columns of memory cells; where a damaged primary column may be replaced by a redundant column, said method comprising: applying a sequence of column addresses to a memory device; and detecting whether a primary column has been replaced by a redundant column at one or more of said column addresses.
Claim 14
Dependent Claim
32 words
A method as recited in claim 10 wherein detecting whether a primary column has been replaced by a redundant column includes detecting whether a redundant column is activated by a column address.
Claim 15
Dependent Claim
28 words
A method as recited in claim 11 further comprising disabling data outputs of said memory cells prior to applying said sequence of column addresses to said memory device.
Claim 16
Dependent Claim
110 words
A memory device comprising: a plurality of primary memory cells arranged into a primary matrix having primary rows and primary columns; a plurality of redundant memory cells arranged into at least one a redundant matrix having redundant rows and redundant columns; addressing means adapted to provide row and column address signals to said primary matrix and said redundant matrix; repair means which, when activated, can disable at least one linear arrangement of primary memory cells and enable at least one linear arrangement of redundant memory cells as a replacement for said disabled linear arrangement of primary cells; and repair detection means for detecting whether said repair means has been activated.
Claim 17
Dependent Claim
110 words
A memory device comprising: a plurality of primary memory cells arranged into a primary matrix having primary rows and primary columns; a plurality of redundant memory cells arranged into at least one a redundant matrix having redundant rows and redundant columns; addressing means adapted to provide row and column address signals to said primary matrix and said redundant matrix; repair means which, when activated, can disable at least one linear arrangement of primary memory cells and enable at least one linear arrangement of redundant memory cells as a replacement for said disabled linear arrangement of primary cells; and repair detection means for detecting whether said repair means has been activated.
Claim 18
Dependent Claim
40 words
A memory device as recited in claim 13 wherein said linear arrangement of primary memory cells and said linear arrangement of redundant memory cells can comprise a row of primary memory cells and a row of redundant memory cells, respectively.
Claim 19
Dependent Claim
41 words
A memory device as recited in claim 14 wherein said linear arrangement of primary memory cells and said linear arrangement of redundant memory cells can further comprise a column of primary memory cells and a column of redundant memory cells, respectively.
Claim 20
Dependent Claim
40 words
A memory device as recited in claim 13 wherein said linear arrangement of primary memory cells and said linear arrangement of redundant memory cells can comprise a column of primary memory cells and a column of redundant memory cells, respectively.
Claim 21
Dependent Claim
43 words
A memory device as recited in claim 13 wherein said repair detection means is coupled to said redundant matrix and is operative to develop a repair detection signal when at least one of said redundant rows and said redundant columns has been enabled.
Claim 22
Dependent Claim
40 words
A memory device as recited in claim 17 wherein said repair detection means is responsive to an enabling signal such that said repair detection signal can only be developed when said enabling signal is applied to said repair detection means.
Claim 23
Dependent Claim
70 words
A memory device as recited in claim 18 further comprising output gating means responsive to a data signal developed by said memory cells, said repair detection signal, and said enabling signal, and operative to develop an output signal reflective of said data signal when said enabling signal is not present, and further operative to develop an output signal reflective of said repair detection signal when said enabling signal is present.
Claim 24
Dependent Claim
66 words
A repair detection circuit for a memory device having a plurality of primary rows of memory cells and at least one redundant row of memory cells, said repair detection circuit comprising: detection means coupled to said redundant row and operative to develop a repair detection signal if said redundant row becomes activated; and enabling means coupled to said detection means for selectively enabling said detection means.
Claim 25
Dependent Claim
66 words
A repair detection circuit for a memory device having a plurality of primary rows of memory cells and at least one redundant row of memory cells, said repair detection circuit comprising: detection means coupled to said redundant row and operative to develop a repair detection signal if said redundant row becomes activated; and enabling means coupled to said detection means for selectively enabling said detection means.
Claim 26
Dependent Claim
51 words
A repair detection circuit as recited in claim 20 wherein said memory device has a plurality of redundant rows, and wherein said detection means is responsive to each of said plurality of redundant rows such that said repair detection signal is developed if any one of said redundant rows becomes activated.
Claim 27
Dependent Claim
58 words
A repair detection circuit as recited in claim 21 wherein said detection means includes a detection comparator responsive to a first reference potential and to a potential developed collectively by said redundant rows, and operative to develop said repair detection signal when said potential developed by said redundant rows has a predetermined relationship to said first reference potential.
Claim 28
Dependent Claim
48 words
A repair detection circuit as recited in claim 22 wherein said enabling means includes an enabling comparator responsive to a second reference potential and to an enabling potential, and operative to enable said detection comparator when said enabling potential has a predetermined relationship to said second reference potential.
Claim 29
Dependent Claim
84 words
A detection circuit comprising: sensing means responsive to a plurality of sensing inputs and operative to develop an sensing signal; detection means responsive to a first reference voltage and to said sensing signal, said detection means being operative to develop a detection signal at a detection node; enabling means responsive to a second reference voltage and an enabling input and having an enabling node which is coupled to said detection node; and a voltage source coupled to said detection node and said enabling node.
Claim 30
Dependent Claim
84 words
A detection circuit comprising: sensing means responsive to a plurality of sensing inputs and operative to develop an sensing signal; detection means responsive to a first reference voltage and to said sensing signal, said detection means being operative to develop a detection signal at a detection node; enabling means responsive to a second reference voltage and an enabling input and having an enabling node which is coupled to said detection node; and a voltage source coupled to said detection node and said enabling node.
Claim 31
Dependent Claim
63 words
A detection circuit as recited in claim 24 wherein said detection means includes a pair of transistors coupled together in a common emitter configuration, where said first reference voltage is applied to the base of a first transistor, said detection input is coupled to the base of a second transistor, and said detection node is coupled to the collector of said first transistor.
Claim 32
Dependent Claim
27 words
A detection circuit as recited in claim 25 wherein said detection means further includes a constant current source coupled to the emitters of said pair of transistors.
Claim 33
Dependent Claim
63 words
A detection circuit as recited in claim 24 wherein said enabling means includes a pair of transistors coupled together in a common emitter configuration, where said second reference voltage is applied to the base of a first transistor, said enabling input is coupled to the base of a second transistor, and said enabling node is coupled to the collector of said first transistor.
Claim 34
Dependent Claim
28 words
A detection circuit as recited in claim 27 wherein said enabling means further includes a first constant current source coupled to the emitters of said pair of transistors.
Claim 35
Dependent Claim
29 words
A detection circuit as recited in claim 28 wherein said enabling means further includes voltage reduction means which couples said enabling input to the base of said second transistor.
Claim 36
Dependent Claim
26 words
A detection circuit as recited in claim 24 wherein said voltage source is coupled to said detection node and said enabling node by current limiting means.
Claim 37
Dependent Claim
27 words
A detection circuit as recited in claim 30 wherein said voltage source is further coupled to said detection node and said enabling node by voltage reduction means.
Claim 38
Dependent Claim
42 words
A detection circuit comprising: sensing means responsive to a plurality of sensing input signals and operative to develop a sensing output signal; and output means responsive to said sensing output signal and an enabling signal, and operative to develop a detection signal.
Claim 39
Dependent Claim
42 words
A detection circuit comprising: sensing means responsive to a plurality of sensing input signals and operative to develop a sensing output signal; and output means responsive to said sensing output signal and an enabling signal, and operative to develop a detection signal.
Claim 40
Dependent Claim
29 words
A detection circuit as recited in claim 32 further comprising comparator means responsive to a comparator input signal and a reference signal, and operative to develop said enabling signal.
Claim 41
Dependent Claim
36 words
A detection circuit as recited in claim 33 wherein said sensing means includes OR gate means having a plurality of inputs responsive to said sensing input signals and an output which develops said sensing output signal.
Claim 42
Dependent Claim
48 words
A detection circuit as recited in claim 34 wherein said output means includes AND gate means having a first input responsive to said enabling signal and having a second input responsive to said sensing output signal, said AND gate means having an output which develops said detection signal.
References Cited (Backward Citations)
No citation records indexed.
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