Patent US5341564A successfully refreshed from Google Patents.
US5341564A
Expired / Lapsed
US
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Method of fabricating integrated circuit module
Assignee: Unisys Corp
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Filing: 1993-05-10
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Granted: 1994-08-30
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Expires: 2013-05-10
Abstract
Abstract An integrated circuit module having microscopic self-alignment features comprises: 1) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof; 2) an interconnect member having a surface which includes input/output pads in a pattern that matches the pattern of pads on the integrated circuit chip; and, 3) one of the surfaces has a predetermined number of holes of one-half to fifty mils deep and the other surface has a predetermined number of protrusions of one-half to fifty mils high which are shaped to fit into the holes and prevent the surfaces from sliding on each other when the input/output pads on both of the surfaces are aligned.
Inventors
- 👤 Mohammad Akhavain
- 👤 Ken W. Economy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:54
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W72/00; H10W72/071; H10W72/072; H10W72/07221; H10W72/07227; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/07254; H10W72/20; H10W72/241; H10W72/242; H10W72/281; H10W72/285; H10W72/287; H10W80/00; H10W80/161; H10W80/168; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A method of fabricating an integrated circuit module which comprises - a) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof, and b) an interconnect member having a surface with input/output pads in a pattern that matches said pattern of pads on said integrated circuit chip; said method including the steps of: forming an electrical insulating layer on one of said surfaces with a predetermined number of holes with vertical sidewalls which encompass said pads on said one surface, and forming a single solder ball on each of said pads on the other surface; randomly placing said solder balls in contact with said insulating layer such that said matching patterns of input/output pads are randomly misaligned with each other; and, sliding said surface with said solder balls parallel to said insulating layer, in random directions, until said solder balls drop into said holes of said insulating layer.
Claim 2
Independent Claim
155 words
A method of fabricating an integrated circuit module which comprises - a) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof, and b) an interconnect member having a surface with input/output pads in a pattern that matches said pattern of pads on said integrated circuit chip; said method including the steps of: forming an electrical insulating layer on one of said surfaces with a predetermined number of holes with vertical sidewalls which encompass said pads on said one surface, and forming a single solder ball on each of said pads on the other surface; randomly placing said solder balls in contact with said insulating layer such that said matching patterns of input/output pads are randomly misaligned with each other; and, sliding said surface with said solder balls parallel to said insulating layer, in random directions, until said solder balls drop into said holes of said insulating layer.
Claim 3
Dependent Claim
26 words
A method according to claim 1 wherein said one surface has multiple holes and said other surface has a single respective solder ball for each hole.
Claim 4
Dependent Claim
28 words
A method according to claim 1 wherein said one surface has multiple holes and said other surface has a respective group of several solder balls for each hole.
Claim 5
Dependent Claim
31 words
A method according to claim 1 wherein said one surface has just a single hole and said other surface has multiple solder balls all of which fit into said single hole.
Claim 6
Dependent Claim
28 words
A method according to claim 1 wherein said insulating layer with said holes is on said interconnect member, and said solder balls are on said integrated circuit chip.
Claim 7
Dependent Claim
28 words
A method according to claim 1 wherein said insulating layer with said holes is on said integrated circuit chip, and said solder balls are on said interconnect member.
Claim 8
Dependent Claim
18 words
A method according to claim 1 wherein said holes in said insulating layer are partially filled with solder.
Claim 9
Dependent Claim
25 words
A method according to claim 1 wherein said holes are one-half to fifty mils deep and said solder balls are one-half to fifty mils high.
Claim 10
Dependent Claim
27 words
A method according to claim 1 wherein said holes are defined by a patterned layer of material selected from photoresist, polyimide, silicon dioxide, silicon nitride, and ceramic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |