Patent US5341096A successfully refreshed from Google Patents.
US5341096A
Expired / Lapsed
US
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Semiconductor integrated circuit having a scan circuit provided with a self-contained signal generator circuit
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1993-07-12
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Granted: 1994-08-23
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Expires: 2013-07-12
Abstract
Abstract A semiconductor integrated circuit device in which a scan circuit is self-contained, is adapted to implement a dynamic burn-in test within an LSI device. The device includes an internal circuit provided in an LSI chip; a scan circuit for delivering scan data into the internal circuit; scan data generation circuit for generating scan data corresponding to a test mode signal; and a clock generation circuit for generating scan clocks corresponding to the test mode signal. In the internal circuit, the scan circuit, the scan data generation circuit and the clock generation circuit are arranged in the LSI chip. Corresponding to the test mode signal, data produced by the scan data generation circuit is delivered to the scan circuit.
Inventors
- 👤 Takeshi Yamamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/31855; G01R31/2851; G01R31/30; G01R31/318555; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
156 words
A semiconductor integrated circuit device comprising: an internal circuit formed of one of a logical circuit and a functional circuit, and said internal circuit including a memory means which inputs scan data supplied via scan path means as address data; scan path means connected to said internal circuit, for delivering scan data into said internal circuit; scan data generation means connected to said scan path means, for generating scan data corresponding to a test mode signal, based on a scan clock output from clock generation means; and clock generation means connected to said scan path means, for generating a scan clock based upon said test mode signal; wherein said internal circuit, said scan path means, said scan data generation means and said clock generation means are formed in a single chip, and the scan data produced by said scan data generation means is delivered to said scan path means in response to said test mode signal.
Claim 2
Dependent Claim
156 words
A semiconductor integrated circuit device comprising: an internal circuit formed of one of a logical circuit and a functional circuit, and said internal circuit including a memory means which inputs scan data supplied via scan path means as address data; scan path means connected to said internal circuit, for delivering scan data into said internal circuit; scan data generation means connected to said scan path means, for generating scan data corresponding to a test mode signal, based on a scan clock output from clock generation means; and clock generation means connected to said scan path means, for generating a scan clock based upon said test mode signal; wherein said internal circuit, said scan path means, said scan data generation means and said clock generation means are formed in a single chip, and the scan data produced by said scan data generation means is delivered to said scan path means in response to said test mode signal.
Claim 3
Dependent Claim
32 words
A semiconductor integrated circuit device according to claim 1, wherein said scan path means comprises a plurality of flip-flops connected to an input terminal and an output terminal of the internal circuit.
Claim 4
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 1, further comprising an input/output circuit which forms an interface with a plurality of external terminals of said internal circuit, and a plurality of flip-flops arranged in a plurality of input/output circuits are connected to each other.
Claim 5
Dependent Claim
62 words
A semiconductor integrated circuit device according to claim 3, wherein data is delivered from an input other than a scan-in pin into an LSI through said flip-flop which is self-contained in said input/output circuit; said scan data is transferred serially through said flip-flop and at the same time delivers said scan data into an LSI from all input terminals through said selector.
Claim 6
Dependent Claim
32 words
A semiconductor integrated circuit device according to claim 1, further comprises a basic clock generation circuit for generating a clock which activates said scan data generation means and said clock generation means.
Claim 7
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 5, wherein said basic clock generation circuit includes a ring oscillator.
Claim 8
Dependent Claim
30 words
A semiconductor integrated circuit device according to claim 5, wherein said scan data generation means produces random pattern data, based upon a clock output from said basic clock generation circuit.
Claim 9
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 5, wherein said scan data generation means is formed by a counter circuit and produces pattern data which is repeatedly inverted based on said clock output from said basic clock generation circuit.
Claim 10
Dependent Claim
128 words
A semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device further comprises an input circuit for a scan-in operation, said input circuit delivers scan test data and clocks delivered from externally in the case of a scan test, to said scan path means, and further includes a selector in said input circuit for a scan-in operation, said selector being activated such that it delivers scan test data supplied to an external terminal in the case of a scan test to said scan path means and delivers data for scanning produced from said scan data generation means and clocks for scanning produced said clock generation means based on said test mode signal in the case of a burn-in operation, to said scan path means.
Claim 11
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 1, wherein said memory means is a synchronous memory circuit which is activated in response to a scan clock delivered from said clock generation means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |