Semiconducteur integrated circuit device having a tester circuit

Claim 1

I. A semiconductor integrated circuit device formed in a single chip comprising: a logic circuit formed by a plurality of combination circuits and sequence circuits; an oscillator circuit receiving an external control signal during a test and generating a clock signal having a predetermined repetitive frequency; a pulse signal generator circuit receiving said clock signal and producing a plurality of test pulse signals having different timings and producing a strobe signal at a predetermined time period; a gate circuit fetching said plurality of test pulse signal in response to incoming test pattern data from an external source in synchronization with said strobe signal and supplying said test pulse signals to said logic circuit; and a register circuit retaining a plurality of output signals of said logic circuit receiving said test pulse signals and outputting said test pulse signals externally as output data.

Claim 3

A system for testing the operation of a semiconductor integrated circuit device formed in a single chip in association with a tester circuit, said system comprising: a logic circuit formed by a plurality of combined circuits and sequence circuits; an oscillator circuit receiving an external control signal during a test and generating a clock signal having a predetermined repetitive frequency; a pulse signal generator circuit receiving said clock signal and producing a plurality of test pulse signals having different timings and producing a strobe signal at a predetermined time period; a gate circuit fetching said plurality of test pulse signal in response to incoming test pattern data from an external source in synchronization with said strobe signal and supplying said test pulse signals to said logic circuit; a register circuit retaining a plurality of output signals of said logic circuit receiving said test pulse signals and outputting said test pulse signals externally as output data; and a tester circuit for testing the normal operation of said semiconductor integrated circuit; a test of said semiconductor integrated circuit being carried out based on a comparison between the output data of said register circuit and a predetermined expected signal output determined by said test pattern data.