Integrated circuit testing arrangements

Claim 1

An integrated circuit testing arrangement comprising: a scan path (5) comprising bistable elements (3A, B, C etc) of the integrated circuit connected, for testing purposes, in a series shift register arrangement, the elements of the scan path each having an output connected to an input of a combinational logic arrangement (1) of the integrated circuit and an input connected to an output of said combinational logic arrangement; a test sequence generator (7) for supplying binary data for clocking into the scan path for test purposes, the generator being arranged to supply sequences of data to the scan path each having a number of bits equal to the number of elements in the scan path; means (10) for clocking the elements of the scan path to cause each element to assume either the same state as the preceding element in the scan path, or to assume the state of the associated output of the combinational logic arrangement, the clocking means being operable to cause alternately the scan path elements to assume the states of the associated outputs of the combinational logic arrangement, and to receive a new sequence of data from said test generator; and means (9) for analysing data clocked out of said scan path as each new sequence of data is received from said generator; characterised in that said generator is arranged to enter successive sequences of data into the scan path so that, for each set of inputs of the combinational logic arrangement which are connected via the combinational .logic arrangement to the same output of the combinational logic arrangement, there are applied to the inputs of that set all possible combinations of different inputs.