Patent US5340758A successfully refreshed from Google Patents.
US5340758A
Expired / Lapsed
US
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Device self-alignment by propagation of a reference structure's topography
Assignee: General Electric Co
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Filing: 1992-08-28
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Granted: 1994-08-23
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Expires: 2012-08-28
Abstract
Abstract A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode to have tapered edges followed by conformal deposition of subsequent layers of the device structure up through a support layer followed by deposition of a subordinate layer such as the source/drain metallization) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the gate conductor using a selective etch method.
Inventors
- 👤 Ching-Yeu Wei
- 👤 George E. Possin
- 👤 Robert F. Kwasnick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; H10D64/00; H10D64/01; H10D64/013
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
251 words
A method of fabricating a thin film transistor in a self-aligned manner comprising the steps of: forming a patterned gate conductor on an upper surface of a substrate, said patterned gate conductor having a selected topography defined by the thickness of said patterned gate conductor above said substrate upper surface and the vertical taper of sidewalls of said patterned gate conductor, said patterned gate conductor being narrower at a top raised portion that is remote from said upper surface of said substrate than it is adjacent to said upper surface of said substrate; depositing a substantially conformal dielectric layer over said patterned gate conductor and exposed portions of said upper surface of said substrate; depositing a substantially conformal layer of semiconductor material over said dielectric layer; depositing a substantially conformal layer of source/drain metallization over said semiconductor material layer; said selected topography being propagated upward through each of the substantially conformal dielectric material, semiconductor material, and source/drain metallization layers; forming a planarization layer of a planarization material over the source/drain metallization, said planarization layer having a substantially planar exposed surface; uniformly removing said planarization material until a portion of said source/drain metallization is exposed that is in substantial alignment with said top raised portion of said gate conductor; selectively etching the exposed source/drain metallization to form source and drain electrodes self aligned to said patterned gate conductor and to expose the underlying semiconductor material, the self-aligned source and drain electrodes being formed without through-the-substrate exposure of photoresist to obtain the self-alignment.
Claim 2
Independent Claim
251 words
A method of fabricating a thin film transistor in a self-aligned manner comprising the steps of: forming a patterned gate conductor on an upper surface of a substrate, said patterned gate conductor having a selected topography defined by the thickness of said patterned gate conductor above said substrate upper surface and the vertical taper of sidewalls of said patterned gate conductor, said patterned gate conductor being narrower at a top raised portion that is remote from said upper surface of said substrate than it is adjacent to said upper surface of said substrate; depositing a substantially conformal dielectric layer over said patterned gate conductor and exposed portions of said upper surface of said substrate; depositing a substantially conformal layer of semiconductor material over said dielectric layer; depositing a substantially conformal layer of source/drain metallization over said semiconductor material layer; said selected topography being propagated upward through each of the substantially conformal dielectric material, semiconductor material, and source/drain metallization layers; forming a planarization layer of a planarization material over the source/drain metallization, said planarization layer having a substantially planar exposed surface; uniformly removing said planarization material until a portion of said source/drain metallization is exposed that is in substantial alignment with said top raised portion of said gate conductor; selectively etching the exposed source/drain metallization to form source and drain electrodes self aligned to said patterned gate conductor and to expose the underlying semiconductor material, the self-aligned source and drain electrodes being formed without through-the-substrate exposure of photoresist to obtain the self-alignment.
Claim 3
Dependent Claim
20 words
The method recited in claim 1 further comprising the step of: providing a back channel passivation layer over the structure.
Claim 4
Dependent Claim
15 words
The method recited in claim 1 wherein: said semiconductor material layer comprises amorphous semiconductor material.
Claim 5
Dependent Claim
46 words
The method recited in claim 3 wherein the step of depositing the semiconductor material comprises: first depositing a layer of substantially undoped amorphous semiconductor material; and second depositing a substantially conformal layer of doped amorphous semiconductor material over said layer of substantially undoped amorphous semiconductor material.
Claim 6
Dependent Claim
36 words
The method recited in claim 4 further comprising performing the following step prior to performing the step of depositing the source/drain metallization: patterning said doped amorphous semiconductor material and said substantially undoped amorphous semiconductor material layers.
Claim 7
Dependent Claim
12 words
The method recited in claim 5 wherein: said semiconductor material is silicon.
Claim 8
Dependent Claim
46 words
The method recited in claim 1 wherein the step of depositing the semiconductor material comprises: first depositing a layer of substantially undoped amorphous semiconductor material; and second depositing a substantially conformal layer of doped amorphous semiconductor material over said layer of substantially undoped amorphous semiconductor material.
Claim 9
Dependent Claim
12 words
The method recited in claim 7 wherein: said semiconductor material is silicon.
Claim 10
Dependent Claim
12 words
The method recited in claim 1 wherein: said semiconductor material is silicon.
Claim 11
Independent Claim
213 words
A method of fabricating a thin film transistor in a self-aligned manner comprising the steps of: forming a gate conductor pattern on an upper surface of a substrate, said gate conductor pattern having a selected topography including substantially vertically tapered sidewalls and a top surface disposed between opposite ones of said sidewalls; depositing a substantially conformal gate dielectric layer over said gate conductor pattern and exposed portions of said substrate surface; depositing a substantially conformal layer of substantially undoped semiconductor material over said gate dielectric layer; depositing a substantially conformal doped layer of semiconductor material over said substantially undoped layer of semiconductor material; depositing a substantially conformal layer of source/drain metallization over said of source/drain metallization over said doped semiconductor material layer; forming a planarization layer of a planarization material over the source/drain metallization, said planarization layer having a substantially planar exposed surface; uniformly removing said planarization material until said source/drain metallization that is in substantial alignment with said gate conductor top surface is exposed; selectively removing the exposed source/drain metallization to expose the underlying doped semiconductor material, such that self-aligned source and drain electrodes are formed without through-the-substrate exposure of photoresist to obtain the self-alignment; removing the doped semiconductor material layer where it has been exposed by removal of said source/drain metallization.
Claim 12
Independent Claim
213 words
A method of fabricating a thin film transistor in a self-aligned manner comprising the steps of: forming a gate conductor pattern on an upper surface of a substrate, said gate conductor pattern having a selected topography including substantially vertically tapered sidewalls and a top surface disposed between opposite ones of said sidewalls; depositing a substantially conformal gate dielectric layer over said gate conductor pattern and exposed portions of said substrate surface; depositing a substantially conformal layer of substantially undoped semiconductor material over said gate dielectric layer; depositing a substantially conformal doped layer of semiconductor material over said substantially undoped layer of semiconductor material; depositing a substantially conformal layer of source/drain metallization over said of source/drain metallization over said doped semiconductor material layer; forming a planarization layer of a planarization material over the source/drain metallization, said planarization layer having a substantially planar exposed surface; uniformly removing said planarization material until said source/drain metallization that is in substantial alignment with said gate conductor top surface is exposed; selectively removing the exposed source/drain metallization to expose the underlying doped semiconductor material, such that self-aligned source and drain electrodes are formed without through-the-substrate exposure of photoresist to obtain the self-alignment; removing the doped semiconductor material layer where it has been exposed by removal of said source/drain metallization.
Claim 13
Dependent Claim
20 words
The method recited in claim 10 further comprising the step of: providing a back channel passivation layer over the structure.
Claim 14
Dependent Claim
34 words
The method recited in claim 10 further comprising performing the following step prior to performing the step of depositing the source/drain metallization: patterning said doped semiconductor material and said substantially undoped amorphous silicon layers.
Claim 15
Dependent Claim
12 words
The method recited in claim 10 wherein: said semiconductor material is silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |