Method and apparatus for standby recovery in a phase locked loop

Claim 3

The method of claim 1 wherein said step of disabling comprises the step of disabling a loop counter means comprising a prescaler and a loop counter.

Claim 4

A standby control circuit for a phase locked loop, comprising: counter enable means for activating or deactivating a counter enable signal, respectively in response to a deactivation or an activation of a standby signal; gating means for providing a voltage controlled oscillator (VCO) output signal at a predetermined logic state in response to a first occurrence of a loop counter output signal after a deactivation of said standby signal, and for providing said VCO output signal in response to a VCO input signal after a first occurrence of a reference counter output signal after said first occurrence of said loop counter output signal; and phase detector enable means for deactivating a phase detector enable signal in response to an activation of said standby signal, and for reactivating said phase detector enable signal in response to said first occurrence of said reference counter output signal after said first occurrence of said loop counter output signal.

Claim 5

A standby control circuit for a phase locked loop, comprising: counter enable means for activating or deactivating a counter enable signal, respectively in response to a deactivation or an activation of a standby signal; gating means for providing a voltage controlled oscillator (VCO) output signal at a predetermined logic state in response to a first occurrence of a loop counter output signal after a deactivation of said standby signal, and for providing said VCO output signal in response to a VCO input signal after a first occurrence of a reference counter output signal after said first occurrence of said loop counter output signal; and phase detector enable means for deactivating a phase detector enable signal in response to an activation of said standby signal, and for reactivating said phase detector enable signal in response to said first occurrence of said reference counter output signal after said first occurrence of said loop counter output signal.

Claim 6

The standby control circuit of claim 3 wherein said counter enable means comprises an inverter having an input terminal for receiving a standby signal, and an output terminal for providing said counter enable signal.

Claim 7

The standby control circuit of claim 3 wherein said gating means comprises: a first D flip-flop having a D input coupled to a first reference voltage representative of a first logic state, a clock input terminal for receiving said loop counter output signal, a set input terminal for receiving said standby signal, and a Q output terminal; a second D flip-flop having a D input coupled to a second reference voltage representative of a second logic state, a clock input terminal for receiving said reference counter output signal, a reset input terminal coupled to said Q output terminal of said first D flip-flop, and a Q output terminal; an OR gate having a first input terminal coupled to said Q output terminal of said first D flip-flop, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal; and an AND gate having a first input terminal coupled to said output terminal of said OR gate, a second input terminal for receiving said VCO input signal, and an output terminal for providing said VCO output signal.

Claim 8

The standby control circuit of claim 5 further comprising delay means coupled to said set input of said first D flip-flop, for providing a predetermined delay between a change in logic state of said standby signal and a change in logic state at said set input of said first D flip-flop.

Claim 9

The standby control circuit of claim 5 wherein said phase detector enable means comprises a second AND gate having a first input terminal for receiving said counter enable signal, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal for providing a phase detector enable signal.

Claim 10

A standby control circuit for a phase locked loop comprising: an inverter having an input terminal for receiving a standby signal, and an output terminal for providing a counter enable signal; a first D flip-flop having a D input coupled to a first reference voltage representative of a first logic state, a clock input terminal for receiving a loop counter output signal, a set input terminal for receiving said standby signal, and a Q output terminal; a second D flip-flop having a D input coupled to a second reference voltage representative of a second logic state, a clock input terminal for receiving a reference counter output signal, a reset input terminal coupled to said Q output terminal of said first D flip-flop, and a Q output terminal; a first AND gate having a first input terminal coupled to said output terminal of said inverter, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal for providing a phase detector enable signal; an OR gate having a first input terminal coupled to said Q output terminal of said first D flip-flop, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal; and a second AND gate having a first input terminal coupled to said output terminal of said OR gate, a second input terminal for receiving a voltage controlled oscillator output signal, and an output terminal for providing a loop counter input signal.

Claim 11

A standby control circuit for a phase locked loop comprising: an inverter having an input terminal for receiving a standby signal, and an output terminal for providing a counter enable signal; a first D flip-flop having a D input coupled to a first reference voltage representative of a first logic state, a clock input terminal for receiving a loop counter output signal, a set input terminal for receiving said standby signal, and a Q output terminal; a second D flip-flop having a D input coupled to a second reference voltage representative of a second logic state, a clock input terminal for receiving a reference counter output signal, a reset input terminal coupled to said Q output terminal of said first D flip-flop, and a Q output terminal; a first AND gate having a first input terminal coupled to said output terminal of said inverter, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal for providing a phase detector enable signal; an OR gate having a first input terminal coupled to said Q output terminal of said first D flip-flop, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal; and a second AND gate having a first input terminal coupled to said output terminal of said OR gate, a second input terminal for receiving a voltage controlled oscillator output signal, and an output terminal for providing a loop counter input signal.

Claim 12

The standby control circuit of claim 8 further comprising delay means coupled to said set input of said first D flip-flop, for providing a predetermined delay between a change in logic state of said standby signal and a change in logic state at said set input of said first D flip-flop.

Claim 13

A phase locked loop comprising: a reference counter having an input for receiving a reference signal, an enable input, and an output for providing a first signal once for each of a first number of cycles of said reference signal; loop counter means having an input for receiving a loop signal, an enable input, and an output for providing a second signal once for each occurrence of a second number of cycles of said loop signal; a phase detector having a first and second inputs respectively receiving said first and second signals, an enable input, and an output for providing a phase detect output signal; a loop filter having an input coupled to said output of said phase detector, and an output; a voltage controlled oscillator (VCO) having an input coupled to said output of said loop filter, and an output for providing a VCO output signal at a frequency proportional to a voltage at said output of said loop filter; and standby control means for activating said counter enable signal in response to a deactivation of said standby signal, for providing said phase detector enable signal in response to said counter enable signal and to said first signal after said deactivation of said standby signal, and for providing said loop signal in response to said VCO signal, after said deactivation of said standby signal and an activation of both said first and second signals.

Claim 14

A phase locked loop comprising: a reference counter having an input for receiving a reference signal, an enable input, and an output for providing a first signal once for each of a first number of cycles of said reference signal; loop counter means having an input for receiving a loop signal, an enable input, and an output for providing a second signal once for each occurrence of a second number of cycles of said loop signal; a phase detector having a first and second inputs respectively receiving said first and second signals, an enable input, and an output for providing a phase detect output signal; a loop filter having an input coupled to said output of said phase detector, and an output; a voltage controlled oscillator (VCO) having an input coupled to said output of said loop filter, and an output for providing a VCO output signal at a frequency proportional to a voltage at said output of said loop filter; and standby control means for activating said counter enable signal in response to a deactivation of said standby signal, for providing said phase detector enable signal in response to said counter enable signal and to said first signal after said deactivation of said standby signal, and for providing said loop signal in response to said VCO signal, after said deactivation of said standby signal and an activation of both said first and second signals.

Claim 15

The phase locked loop of claim 10 wherein said standby control circuit comprises: an inverter having an input terminal for receiving a standby signal, and an output terminal for providing a counter enable signal; a first D flip-flop having a D input coupled to a first reference voltage representative of a first logic state, a clock input terminal for receiving a loop counter output signal, a set input terminal for receiving said standby signal, and a Q output terminal; a second D flip-flop having a D input coupled to a second reference voltage representative of a second logic state, a clock input terminal for receiving a reference counter output signal, a reset input terminal coupled to said Q output terminal of said first D flip-flop, and a Q output terminal; a first AND gate having a first input terminal coupled to said output terminal of said inverter, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal for providing a phase detector enable signal; an OR gate having a first input terminal coupled to said Q output terminal of said first D flip-flop, a second input terminal coupled to said Q output terminal of said second D flip-flop, and an output terminal; and a second AND gate having a first input terminal coupled to said output terminal of said OR gate, a second input terminal for receiving said VCO output signal, and an output terminal for providing said loop signal.

Claim 16

The phase locked loop of claim 11 further comprising delay means coupled to said set input of said first D flip-flop, for providing a predetermined delay between a change in logic state of said standby signal and a change in logic state at said set input of said first D flip-flop.