Phase-locked loop frequency synthesizer having reduced power consumption

Claim 1

A phase-locked loop frequency synthesizer comprising an oscillator for producing a reference frequency, a fixed divider for dividing the reference frequency by a predetermined dividing ratio, a voltage-controlled oscillator for producing a frequency proportional to a DC voltage to be input thereto, a programmable divider for dividing frequencies to be output from said voltage-controlled oscillator by a programmed dividing ratio, a phase detector for detecting the difference of frequencies and phases in the outputs from said fixed and programmable dividers to produce said DC voltage, and means for intermittently interrupting said phase-locked loop to change it into an open loop, wherein there are provided first means positioned between said oscillator and said fixed divider for interrupting the input of said reference frequency to said fixed divider, and second means positioned between said voltage-controlled oscillator and said programmable divider for interrupting the input of said frequencies therefrom to said programmable divider respectively whereby said fixed and programmable dividers preserve counting values thereof when said first and second means interrupt said inputs thereto at the time of changing from a phase-locked loop to an open loop.