Frequency synthesizer

Claim 2

A programmable frequency divider circuit includ­ing a division ratio data generator and a programmable counter which varied the division ratio with the output from said division ratio data generator which is character­ized in that it further comprises a control circuit which variably sets the division ratio to be generated from said division ratio data generator, and that said control circuit includes a means which can set the division ratio data n as the division ratio for the dividing operation for the first cycle after the reset condition is released in said programmable counter and sets another division ratio data m which is different from said n as the division ratio for dividing operation for the second cycle and thereafter.

Claim 3

The programmable frequency divider circuit as claimed in Claim 1 which further comprises a division ratio data latch circuit provided between the division ratio data generator and the programmable counter which can retain the division ratio data temporarily, and which sends the division ratio data to said programmable counter when a trigger signal is sent out from the control circuit.

Claim 4

The programmable frequency divider circuit as claimed in Claim 1 which is characterized in that the programmable counter includes a means which takes in the division ratio data from the division ratio data generator when the reset condition is released and when the dividing operation for one cycle is completed.

Claim 5

A frequency synthesizer comprising a voltage controlled oscillator, variable frequency divider which receives the output from said voltage controlled oscillator as an input, divides frequency with the division ratio n for the first cycle after the release of reset condition and with the divi­sion ratio N for the second cycle and thereafter, a phase comparator which compares the output signals of the variable frequency divider with the output signals from a reference signal oscillator, a loop filter which smoothes the output from said phase comparator to input it to said voltage controlled oscillator, and a phase detector which detects the phase difference between the output signals from said variable frequency divider and the output signals from said reference signal oscillator to control a loop formed with a switch circuit which blocks the phase difference signals of said phase comparator from said loop filter, which is characterized in that when a loop is formed, the control voltage of the voltage control oscillator corresponding to the output oscillation frequency is latched at the loop filter the internal condition of said variable frequency divider is reset by setting n₁ as the division ratio n before closing the loop as the first phase difference detection, then an edge of the output from said reference signal oscillator is detected to release the reset condition of said variable frequency divider to divide frequency with n₁ for the first cycle alone, and with N for the second cycle and thereafter, the phase difference between the output phase from said reference signal oscillator and the N-divided output phase from said variable frequency divider is detected by said phase difference detector during said frequency dividing operation, the division ratio n₂ is set for said variable frequency divider based on the result of detection, condition of said variable frequency divider is reset again as the second phase difference detection to repeat the operation similar to the first detection until the time the phase difference between the output phase of said reference oscillator and the output phase from the variable frequency divider becomes smaller than the reference value, and then the loop is finally closed.

Claim 6

A frequency synthesizer comprising a voltage controlled oscillator, variable frequency divider which receives the output from said voltage controlled oscillator as an input, divides frequency with the division ratio n for the first cycle after the release of reset condition and with the divi­sion ratio N for the second cycle and thereafter, a phase comparator which compares the output signals of the variable frequency divider with the output signals from a reference signal oscillator, a loop filter which smoothes the output from said phase comparator to input it to said voltage controlled oscillator, and a phase detector which detects the phase difference between the output signals from said variable frequency divider and the output signals from said reference signal oscillator to control a loop formed with a switch circuit which blocks the phase difference signals of said phase comparator from said loop filter, which is characterized in that when a loop is formed, the control voltage of the voltage control oscillator corresponding to the output oscillation frequency is latched at the loop filter the internal condition of said variable frequency divider is reset by setting n₁ as the division ratio n before closing the loop as the first phase difference detection, then an edge of the output from said reference signal oscillator is detected to release the reset condition of said variable frequency divider to divide frequency with n₁ for the first cycle alone, and with N for the second cycle and thereafter, the phase difference between the output phase from said reference signal oscillator and the N-divided output phase from said variable frequency divider is detected by said phase difference detector during said frequency dividing operation, the division ratio n₂ is set for said variable frequency divider based on the result of detection, condition of said variable frequency divider is reset again as the second phase difference detection to repeat the operation similar to the first detection until the time the phase difference between the output phase of said reference oscillator and the output phase from the variable frequency divider becomes smaller than the reference value, and then the loop is finally closed.

Claim 7

A frequency synthesizer arranged to generate an output signal at a set frequency which is a multiple of the frequency of a reference signal characterized in that the frequency synthesizer is arranged to establish the set frequency signal with a phase difference less than a set level relative to the reference signal by generating, for a period, an output signal of frequency providing phase movement relative to the reference signal and to terminate operation at the frequency providing phase movement by switching to the set frequency.

Claim 8

A frequency synthesizer arranged to generate an output signal at a set frequency which is a multiple of the frequency of a reference signal characterized in that the frequency synthesizer is arranged to establish the set frequency signal with a phase difference less than a set level relative to the reference signal by generating, for a period, an output signal of frequency providing phase movement relative to the reference signal and to terminate operation at the frequency providing phase movement by switching to the set frequency.

Claim 9

A frequency synthesizer as claimed in claim 6, arranged to maintain operation at the set frequency while the phase difference between the set frequency signal and the reference signal remains at less than the set level and to revert to operation with phase movement for a further period if the phase difference exceeds the set level.

Claim 10

A frequency synthesizer as claimed in claim 6, arranged to revert, during the further period, to the generation of the same frequency signal as used previously for providing phase movement.

Claim 11

A frequency synthesizer as claimed in claim 6, arranged to revert, during the further period, to the generation of a signal of frequency different from that used previously for providing phase movement.

Claim 12

A frequency synthesizer as claimed in any one of claims 5 to 8, in which each period of operation with phase movement is set by means of a first arrangement for counting a set number of cycles of the signal providing the phase movement and indicating when the set count has been reached.

Claim 13

A frequency synthesizer as claimed in claim 9, in which the first arrangement for counting a set number of cycles of the signal providing phase movement belongs to a dividing and counting circuit forming part of the synthesizer control system.

Claim 14

A frequency synthesizer as claimed in claim 10, in which the dividing and counting circuit includes a dual-module dividing circuit arranged to drive the first and a second arrangement for counting, and the dividing circuit and the first counting circuit are so inter-­connected that the dividing circuit operates with a first division ratio until the count of the first arrangement for counting reaches the set number after which the dividing circuit is altered to operate with a second division ratio.

Claim 15

A frequency synthesizer as claimed in any one of claims 5 to 11, including a voltage controlled oscillator, a control system for the oscillator, and means for switching on and switching off the control system, in which, in operation of the controlled oscillator at the frequency providing phase movement relative to the reference signal and is switched on briefly, and, at the end of the period of operation with phase movement, the control system is arranged to effect the operation of the controlled oscillator at the set frequency and is switched on indefinitely.

Claim 16

A frequency synthesizer comprising a voltage controlled oscillator and a control loop for the voltage controlled oscillator in which the control loop includes a variable frequency divider connected to receive the output signal from the voltage controlled oscillator as an input signal, and is arranged to operate initially with a division ratio n after the release of a reset condition, and, thereafter, to operate with a division ratio N .

Claim 17

A frequency synthesizer comprising a voltage controlled oscillator and a control loop for the voltage controlled oscillator in which the control loop includes a variable frequency divider connected to receive the output signal from the voltage controlled oscillator as an input signal, and is arranged to operate initially with a division ratio n after the release of a reset condition, and, thereafter, to operate with a division ratio N .

Claim 18

A dividing and counting circuit including a dual-modulus dividing circuit arranged to drive a first and a second counting arrangement, the dividing circuit and the first counting circuit operates with a first division ratio until the count of the first counting arrangement reaches a set number after which the dividing circuit is altered by its connection to the first counting circuit to operate with a second division ratio.

Claim 19

A dividing and counting circuit including a dual-modulus dividing circuit arranged to drive a first and a second counting arrangement, the dividing circuit and the first counting circuit operates with a first division ratio until the count of the first counting arrangement reaches a set number after which the dividing circuit is altered by its connection to the first counting circuit to operate with a second division ratio.

Claim 20

A dividing and counting circuit as claimed in claim 14, in which the second counting arrangement is a programmable counter.

Claim 21

A dividing and counting circuit as claimed in claim 14 or claim 15, in which the first counting arrangement is a programmable counter.