Method of fabricating BiCMOS device

Claim 1

A method of forming semiconductor devices including a gate insulating region for a field effect gate, wherein said semiconductor devices include a bipolar transistor formed in a first region, an n-channel field effect (NMOS) transistor formed in a second region, and a p-channel field effect (PMOS) transistor formed in a third region, said method comprising the steps of: in a p-type semiconductor substrate, masking and implanting n-type dopants for formations of an n-type buried layer for said PMOS and bipolar transistors; masking and implanting p-type dopants for formation of a p-type buried layer for said NMOS transistor and p-type channel stops adjacent said first region; forming an n-type epitaxial silicon layer on said substrate; forming field oxide regions adjacent said first, said second and said third regions, as well as between a sink and a base region of said first region; masking and implanting n-type dopants into said sink region to a first dopant concentration; masking and implanting n-type dopants into said third region to a second dopant concentration; and masking and implanting p-type dopants into said second and third regions so as to adjust a threshold voltage of said NMOS and PMOS transistors; forming an insulator region on a surface of a semiconductor substrate, comprising forming a gate oxide layer on said epitaxial layer; forming a first polysilicon layer on said insulator; forming a mask on portions of said polysilicon layer, said portions defining gate regions of field effect devices, comprising masking said first layer of polysilicon and said oxide layer to define gate oxide regions for said NMOS and PMOS transistors; removing said polysilicon and said insulator from said surface in regions not protected by said mask; forming a conductive region along said surface above said insulator region, comprising forming a second layer of polysilicon on said first layer of polysilicon and said epitaxial layer; etching said conductive region to form said gate in said gate regions above said insulator regions, comprising masking and implanting n-type and p-type dopants into said second polysilicon layer and etching said polysilicon layer to form emitter, base, collector contacts for said bipolar transistor; source and drain contacts for said NMOS and PMOS transistors; and gate polysilicon regions for said NMOS and PMOS transistors; said method further comprising thereafter the steps of implanting n-type dopant to form a lightly doped diffusion in said NMOS transistor; masking and implanting Boron to form a lightly doped diffusion for PMOS and bipolar transistors; forming sidewall oxide on said emitter, base, collector contacts of said bipolar transistor, said source and drain contacts of said NMOS and PMOS transistors, and said gate polysilicon regions of said NMOS and PMOS transistors; masking said sidewall oxide on said emitter contact and said gate polysilicon regions and removing sidewall oxide from exposed regions; implanting p-type dopants into said first and third regions; implanting n-type dopants into said second regions; forming a refractory metal layer across at least said first, second and third regions and heating said substrate so as to form metal silicide where said refractory metal contacts silicon; removing unreacted metal from at least said first, said second, and said third regions; and forming an interconnect system for said NMOS, said PMOS and said bipolar transistors.

Claim 2

A method of forming semiconductor devices including a gate insulating region for a field effect gate, wherein said semiconductor devices include a bipolar transistor formed in a first region, an n-channel field effect (NMOS) transistor formed in a second region, and a p-channel field effect (PMOS) transistor formed in a third region, said method comprising the steps of: in a p-type semiconductor substrate, masking and implanting n-type dopants for formations of an n-type buried layer for said PMOS and bipolar transistors; masking and implanting p-type dopants for formation of a p-type buried layer for said NMOS transistor and p-type channel stops adjacent said first region; forming an n-type epitaxial silicon layer on said substrate; forming field oxide regions adjacent said first, said second and said third regions, as well as between a sink and a base region of said first region; masking and implanting n-type dopants into said sink region to a first dopant concentration; masking and implanting n-type dopants into said third region to a second dopant concentration; and masking and implanting p-type dopants into said second and third regions so as to adjust a threshold voltage of said NMOS and PMOS transistors; forming an insulator region on a surface of a semiconductor substrate, comprising forming a gate oxide layer on said epitaxial layer; forming a first polysilicon layer on said insulator; forming a mask on portions of said polysilicon layer, said portions defining gate regions of field effect devices, comprising masking said first layer of polysilicon and said oxide layer to define gate oxide regions for said NMOS and PMOS transistors; removing said polysilicon and said insulator from said surface in regions not protected by said mask; forming a conductive region along said surface above said insulator region, comprising forming a second layer of polysilicon on said first layer of polysilicon and said epitaxial layer; etching said conductive region to form said gate in said gate regions above said insulator regions, comprising masking and implanting n-type and p-type dopants into said second polysilicon layer and etching said polysilicon layer to form emitter, base, collector contacts for said bipolar transistor; source and drain contacts for said NMOS and PMOS transistors; and gate polysilicon regions for said NMOS and PMOS transistors; said method further comprising thereafter the steps of implanting n-type dopant to form a lightly doped diffusion in said NMOS transistor; masking and implanting Boron to form a lightly doped diffusion for PMOS and bipolar transistors; forming sidewall oxide on said emitter, base, collector contacts of said bipolar transistor, said source and drain contacts of said NMOS and PMOS transistors, and said gate polysilicon regions of said NMOS and PMOS transistors; masking said sidewall oxide on said emitter contact and said gate polysilicon regions and removing sidewall oxide from exposed regions; implanting p-type dopants into said first and third regions; implanting n-type dopants into said second regions; forming a refractory metal layer across at least said first, second and third regions and heating said substrate so as to form metal silicide where said refractory metal contacts silicon; removing unreacted metal from at least said first, said second, and said third regions; and forming an interconnect system for said NMOS, said PMOS and said bipolar transistors.