US5179031A
Expired / Lapsed
US
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Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
Assignee: National Semiconductor Corp
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Filing: 1990-07-19
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Granted: 1993-01-12
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Expires: 2010-07-19
Abstract
Abstract A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.
Inventors
- 👤 Michael P. Brassington
- 👤 Reda R. Razouk
- 👤 Monir H. El-Diwany
- 👤 Prateep Tuntasood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:20
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
166 words
A method of making a polysilicon emitter simultaneously with a polysilicon gate in a semiconductor device comprising the steps of: growing a thin layer of an oxide on emitter and gate regions of a silicon substrate; depositing a thin layer of polysilicon of from 500 angstroms to approximately 1000 angstroms on the oxide layer; removing the thin polysilicon layer from the emitter region of the silicon substrate; removing the oxide layer from the emitter region of the silicon substrate; depositing a thick layer of polysilicon of from approximately 2200 angstroms to approximately 2800 angstroms on the emitter and gate regions of the silicon substrate; masking the emitter and gate regions for defining a respective polysilicon emitter and polysilicon gate; and simultaneously etching the polysilicon from the emitter and gate regions for simultaneously forming the respective polysilicon emitter and polysilicon gate, wherein a portion of the substrate adjacent to the polysilicon emitter is etched to a depth approximately equal to the depth of the thin polysilicon layer.
Claim 2
Independent Claim
166 words
A method of making a polysilicon emitter simultaneously with a polysilicon gate in a semiconductor device comprising the steps of: growing a thin layer of an oxide on emitter and gate regions of a silicon substrate; depositing a thin layer of polysilicon of from 500 angstroms to approximately 1000 angstroms on the oxide layer; removing the thin polysilicon layer from the emitter region of the silicon substrate; removing the oxide layer from the emitter region of the silicon substrate; depositing a thick layer of polysilicon of from approximately 2200 angstroms to approximately 2800 angstroms on the emitter and gate regions of the silicon substrate; masking the emitter and gate regions for defining a respective polysilicon emitter and polysilicon gate; and simultaneously etching the polysilicon from the emitter and gate regions for simultaneously forming the respective polysilicon emitter and polysilicon gate, wherein a portion of the substrate adjacent to the polysilicon emitter is etched to a depth approximately equal to the depth of the thin polysilicon layer.
Claim 3
Dependent Claim
75 words
The method according to claim 1 wherein the polysilicon layer removing step comprises the steps of: depositing a photoresist layer as a blanket coating above the thin polysilicon layer; developing the photoresist layer for forming an opening in the photoresist layer for exposing the portion of the polysilicon layer above the emitter region; and etching the exposed portion of the polysilicon layer for exposing the portion of the gate oxide layer above the emitter region.
Claim 4
Dependent Claim
37 words
The method according to claim 2 wherein the gate oxide layer removing step comprises the steps of: retaining the photoresist layer; and etching the exposed portion of the gate oxide layer in a buffered oxide etching solution.
Claim 5
Dependent Claim
49 words
The method according to claim 3 wherein the gate oxide growing step comprises the step of: growing a layer of silicon dioxide on emitter and gate regions of the silicon substrate, the silicon dioxide having a thickness in the range of from approximately 150 angstroms to approximately 300 angstroms.
Claim 6
Dependent Claim
39 words
The method according to claim 5 further comprising the steps of: depositing a conformal oxide layer as a blanket coating over the silicon substrate; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 7
Independent Claim
320 words
A method of simultaneously making a polysilicon emitter with a polysilion gate in a semiconductor device comprising the steps of: forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region; forming a MOS region in the silicon substrate for a MOS device, the MOS region being separate from the bipolar region by a second field oxide region; forming a thin gate oxide layer on the bipolar region and on the MOS region; forming a thin polysilicon layer of from 500 angstroms to approximately 1000 angstroms on the bipolar region and on the MOS region; removing the thin polysilicon layer from the second region; removing the thin gate oxide layer from the second region; depositing a thick polysilicon layer of from approximately 2200 angstroms to approximately 2800 angstroms on the bipolar region and on the MOS region; masking a portion of the second region for forming a polysilicon emitter; masking a portion of the MOS region for forming a polysilicon gate; simultaneously etching the polysilicon from the bipolar region and from the MOS region other than from the masked portions of the bipolar region and the MOS region for forming a respective polysilicon emitter and polysilicon gate wherein a portion of the substrate adjacent to the polysilicon emitter is etched to a depth approximately equal to the depth of the thin polysilicon layer; removing the thin gate oxide layer from the collector region; doping the collector region and the MOS region to a first conductivity type; doping the second region to a conductivity type opposite the conductivity type of the collector region; depositing a conformal oxide layer on the bipolar region and on the MOS region; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 8
Independent Claim
320 words
A method of simultaneously making a polysilicon emitter with a polysilion gate in a semiconductor device comprising the steps of: forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region; forming a MOS region in the silicon substrate for a MOS device, the MOS region being separate from the bipolar region by a second field oxide region; forming a thin gate oxide layer on the bipolar region and on the MOS region; forming a thin polysilicon layer of from 500 angstroms to approximately 1000 angstroms on the bipolar region and on the MOS region; removing the thin polysilicon layer from the second region; removing the thin gate oxide layer from the second region; depositing a thick polysilicon layer of from approximately 2200 angstroms to approximately 2800 angstroms on the bipolar region and on the MOS region; masking a portion of the second region for forming a polysilicon emitter; masking a portion of the MOS region for forming a polysilicon gate; simultaneously etching the polysilicon from the bipolar region and from the MOS region other than from the masked portions of the bipolar region and the MOS region for forming a respective polysilicon emitter and polysilicon gate wherein a portion of the substrate adjacent to the polysilicon emitter is etched to a depth approximately equal to the depth of the thin polysilicon layer; removing the thin gate oxide layer from the collector region; doping the collector region and the MOS region to a first conductivity type; doping the second region to a conductivity type opposite the conductivity type of the collector region; depositing a conformal oxide layer on the bipolar region and on the MOS region; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 9
Dependent Claim
75 words
The method according to claim 6 wherein the polysilicon layer removing step comprises the steps of: depositing a photoresist layer as a blanket coating over the thin polysilicon layer; developing the photoresist layer for forming an opening in the photoresist layer for exposing the portion of the polysilicon layer above the emitter region; and etching the exposed portion of the polysilicon layer for exposing the portion of the gate oxide layer above the emitter region.
Claim 10
Dependent Claim
37 words
The method according to claim 7 wherein the gate oxide layer removing step comprises the steps of: retaining the photoresist layer; and etching the exposed portion of the gate oxide layer in a buffered oxide etching solution.
Claim 11
Dependent Claim
49 words
The method according to claim 8 wherein the gate oxide growing step comprises the step of: growing a layer of silicon dioxide on emitter and gate regions of the silicon substrate, the silicon dioxide having a thickness in the range of from approximately 150 angstroms to approximately 300 angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |