Patent US5337024A successfully refreshed from Google Patents.
US5337024A
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Phase locked loop frequency modulator using fractional division
Assignee: Boeing North American Inc
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Filing: 1993-06-22
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Granted: 1994-08-09
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Expires: 2013-06-22
Abstract
Abstract A frequency modulation circuit includes a phase-locked loop having a reference frequency input and a controlled frequency output. The phase-locked loop has a phase detector, a filter and a voltage-controlled oscillator and, in a feedback path between the output and the phase detector, a frequency divider. Also included is a converter converting an input signal to a digital modulation signal M, and an adder inverting the most significant bit of the digital modulation signal and adding it to a digital word representing a selected frequency. The frequency divider divides a fractional number (N.F)±M, where N is an integer, F is a fraction and M is the digital value of modulation data. This configuration is advantageous because data can be taken directly from the analog-to-digital output to the adder with no data translation, the modulation signal M could also be provided from a processor data bus, the peak deviation is selectable, and no carrier offset results from injecting the modulation signal into the phase-locked loop.
Inventors
- 👤 Ray L. Collins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:07
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; H03C3/0908; H03C3/0916; H03C3/0933; H03C3/0925; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
140 words
A frequency modulation circuit, comprising: a phase-locked loop having a reference frequency input and a controlled frequency output, the phase-locked loop having a phase detector, a filter and a voltage-controlled oscillator, the phase-locked loop also having a frequency divider in a feedback path between the output and the phase detector; a circuit providing a digital modulation signal M; an adder, responsive to the digital modulation signal M and a first digital word F representing a selected frequency, the adder inverting the most significant bit of the digital modulation signal M and providing a second digital word; and in response to the adder providing the second digital word, the frequency divider dividing the controlled frequency output by a fractional number Y.X, where Y is an integer part of the fractional number, and X is a fractional part of the fractional number.
Claim 2
Dependent Claim
140 words
A frequency modulation circuit, comprising: a phase-locked loop having a reference frequency input and a controlled frequency output, the phase-locked loop having a phase detector, a filter and a voltage-controlled oscillator, the phase-locked loop also having a frequency divider in a feedback path between the output and the phase detector; a circuit providing a digital modulation signal M; an adder, responsive to the digital modulation signal M and a first digital word F representing a selected frequency, the adder inverting the most significant bit of the digital modulation signal M and providing a second digital word; and in response to the adder providing the second digital word, the frequency divider dividing the controlled frequency output by a fractional number Y.X, where Y is an integer part of the fractional number, and X is a fractional part of the fractional number.
Claim 3
Dependent Claim
26 words
A frequency modulation circuit, according to claim 1, wherein the adder adds the value of the digital modulation signal M, to the first digital word F.
Claim 4
Dependent Claim
48 words
A frequency modulation circuit, according to claim 1, wherein the adder converts the digital modulation signal M by inverting its most significant bit so that the converted digital modulation signal has a value that is set for modulation arithmetic around a digital value corresponding to a center frequency.
Claim 5
Dependent Claim
48 words
A frequency modulation circuit, according to claim 3, wherein the adder adds the converted digital modulation signal to the first digital word F; and sign extends the inverted most significant bit of the converted digital modulation signal up to the most significant bit of the input frequency word.
Claim 6
Dependent Claim
43 words
A frequency modulation circuit, according to claim 1, wherein the circuit providing the digital modulation signal includes an analog-to-digital converter, and the digital modulation signal M is provided from the analog-to-digital converter with no translation or special processing of the digital modulation signal.
Claim 7
Dependent Claim
74 words
A frequency modulation circuit, according to claim 1, wherein the adder converts the digital modulation signal M by inverting its most significant bit so that the converted digital modulation signal is a signed value that is set around a digital value of zero magnitude corresponding to a center frequency, the adder sign extends the inverted most significant bit, and the adder adds the converted digital modulation signal M to the first digital word F.
Claim 8
Dependent Claim
36 words
A frequency modulation circuit, according to claim 6, wherein when the adder adds the converted digital modulation signal M to the first digital word F, an overflow therefrom results in the addition of a carryover bit.
Claim 9
Dependent Claim
41 words
A frequency modulation circuit, according to claim 6, wherein the circuit providing the digital modulation signal includes an analog-to-digital converter and the digital modulation signal M is provided from the analog-to-digital converter with no translation of the digital modulation signal M.
Claim 10
Dependent Claim
43 words
A frequency modulation circuit, according to claim 1, wherein the adder converts the digital modulation signal M by inverting its most significant bit, sign extends the inverted most significant bit, and adds the converted digital modulation signal M to a fractional number N.F.
Claim 11
Dependent Claim
30 words
A frequency modulation circuit, according to claim 1, wherein the signal M has a bit length less than the bit length of the fractional part of the fractional number Y.X.
Claim 12
Dependent Claim
25 words
A frequency modulation circuit, according to claim 10, wherein the signal M is shifted before said adding so as to set a desired deviation level.
Claim 13
Dependent Claim
158 words
A frequency modulation circuit, comprising: a phase-locked loop having a reference frequency input and a controlled frequency output, the phase-locked loop having a phase detector, a filter and a voltage-controlled oscillator, the phase-locked loop also having a frequency divider in a feedback path between the output and the phase detector; an analog-to-digital converter providing a digital modulation signal M; and an adder, receiving the digital modulation signal M and a first digital word F representing a selected frequency, converting the digital modulation signal M by inverting its most significant bit, sign extending the inverted most significant bit to provide a modified signal, and adding the modified digital modulation signal to a fractional number N.F so as to provide a digital sum thereof Y.X, where N is an integer part and F is a fractional part of the fractional number corresponding to a selected frequency; wherein the frequency divider divides the controlled frequency output by the fractional number Y.X.
Claim 14
Dependent Claim
158 words
A frequency modulation circuit, comprising: a phase-locked loop having a reference frequency input and a controlled frequency output, the phase-locked loop having a phase detector, a filter and a voltage-controlled oscillator, the phase-locked loop also having a frequency divider in a feedback path between the output and the phase detector; an analog-to-digital converter providing a digital modulation signal M; and an adder, receiving the digital modulation signal M and a first digital word F representing a selected frequency, converting the digital modulation signal M by inverting its most significant bit, sign extending the inverted most significant bit to provide a modified signal, and adding the modified digital modulation signal to a fractional number N.F so as to provide a digital sum thereof Y.X, where N is an integer part and F is a fractional part of the fractional number corresponding to a selected frequency; wherein the frequency divider divides the controlled frequency output by the fractional number Y.X.
Claim 15
Dependent Claim
29 words
A frequency modulation circuit, according to claim 12, wherein the signal M has a bit length less than the bit length of fractional part of the fractional number N.F.
Claim 16
Dependent Claim
25 words
A frequency modulation circuit, according to claim 13, wherein the signal M is shifted before said adding so as to set a desired deviation level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |