Fractional-N synthesizer having modulation spur compensation

Claim 2

A frequency synthesizer for providing a modulated output frequency f out comprising: a synthesizer loop including: a voltage controlled oscillator for providing the output frequency f out , said output frequency being f out =K* f ref where K=the loop divisor; a programmable fractional loop divider for dividing the output frequency f out by a fractional modulus J, said fractional modulus J=M+N/D where: M=integer divisor N=fractional numerator D=fractional denominator; said programmable divider including compensation means for reducing the generated spurs of the frequency synthesizer when N is equal to a non-zero integer, modulation means for varying said modulus in accordance with a modulating signal and providing the loop divisor K; a fractional reference divider having a reference divider ratio R for dividing an oscillator frequency and providing a reference frequency f ref ; and means for selecting a reference divisor R, whereby a non-zero fractional numerator N is produced.

Claim 3

The frequency synthesizer of claim 1, wherein said reference divisor R is selected such that said generated spurs are below the side band noise limits of the voltage controlled oscillator.

Claim 4

The frequency synthesizer as defined in claim 1, wherein said means for selecting said reference divisor includes a memory means, the memory means having stored therein output frequency informations N,M, and D as well as the reference divisor R.

Claim 5

A radio including a synthesizer for providing modulated and unmodulated local oscillator output frequency f out ; said synthesizer comprising: a synthesizer loop including: a voltage controlled oscillator for providing the output frequency f out , said output frequency being f out =K* f ref where K=the loop divisor ; a programmable fractional loop divider for dividing the output frequency f out by a fractional modulus J, said fractional modulus J=M+N/D where: M=integer divisor N=fractional numerator D=fractional denominator; said programmable divider including compensation means for reducing the generated spurs of the frequency synthesizer when N is equal to a non-zero integer, modulation means for varying said modulus in accordance with a modulating signal and providing the loop divisor K; a fractional reference divider having a reference divider ratio R for dividing an oscillator frequency and providing a reference frequency f ref ; and means for selecting a reference divisor R, whereby a non-zero fractional numerator N is produced.

Claim 6

A radio including a synthesizer for providing modulated and unmodulated local oscillator output frequency f out ; said synthesizer comprising: a synthesizer loop including: a voltage controlled oscillator for providing the output frequency f out , said output frequency being f out =K* f ref where K=the loop divisor ; a programmable fractional loop divider for dividing the output frequency f out by a fractional modulus J, said fractional modulus J=M+N/D where: M=integer divisor N=fractional numerator D=fractional denominator; said programmable divider including compensation means for reducing the generated spurs of the frequency synthesizer when N is equal to a non-zero integer, modulation means for varying said modulus in accordance with a modulating signal and providing the loop divisor K; a fractional reference divider having a reference divider ratio R for dividing an oscillator frequency and providing a reference frequency f ref ; and means for selecting a reference divisor R, whereby a non-zero fractional numerator N is produced.

Claim 7

The radio of claim 4, wherein said reference divisor R is selected such that said generated spurs are below the side band noise limits of the voltage controlled oscillator.

Claim 8

The radio of claim 4, wherein said means for selecting said reference divisor includes a memory means, the memory means having stored therein output frequency informations N, M, and D as well as the reference divisor R.