Semiconductor integrated circuit device having analog circuit and digital circuit formed on one chip

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type formed in said semiconductor substrate; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; and bias means for biasing said semiconductor substrate by a constant potential, said bias means including a semiconductor region of the first conductivity type formed is that portion of said semiconductor substrate which lies between said first and second well regions and having an impurity concentration higher than said semiconductor substrate, a potential supplying source, and a power source line connected between said semiconductor region and said potential supplying source.

Claim 3

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type formed in said semiconductor substrate; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; a third well region of the first conductivity type formed in said first well region and a fourth well region of the first conductivity type formed in said second well region; and first bias means for biasing said third well region by a constant potential and second bias means for biasing said fourth well region by a constant potential, said first bias means including a first semiconductor region of the first conductivity type formed in said third well region and having an impurity concentration higher than said third well region, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, and said second bias means including a second semiconductor region of the first conductivity type formed in said fourth well region and having an impurity concentration higher than said fourth well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region.

Claim 4

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type formed in said semiconductor substrate; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; a third well region of the first conductivity type formed in said first well region and a fourth well region of the first conductivity type formed in said second well region; and first bias means for biasing said third well region by a constant potential and second bias means for biasing said fourth well region by a constant potential, said first bias means including a first semiconductor region of the first conductivity type formed in said third well region and having an impurity concentration higher than said third well region, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, and said second bias means including a second semiconductor region of the first conductivity type formed in said fourth well region and having an impurity concentration higher than said fourth well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region.

Claim 5

A device according to claim 2, further comprising a third semiconductor region of the second conductivity type formed in said third well region and acting as part of an active element; a third potential supplying source; a third power source line connected between said third semiconductor region and said third potential supplying source; a fourth semiconductor region of the second conductivity type formed in said fourth well region and acting as part of an active element; a fourth potential supplying source; a fourth power source line connected between said fourth semiconductor region and said fourth potential supplying source.

Claim 6

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; first bias means for biasing said semiconductor substrate by a constant potential; a first well region of a second conductivity type formed in said semiconductor substrate, a digital circuit being formed in said first well region; second bias means for biasing said first well region by a constant potential; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; and third bias means for biasing said second well region by a constant potential, wherein said first bias means includes a first semiconductor region of the first conductivity type formed in that portion of said semiconductor substrate which lies between said first and second well regions and having an impurity concentration higher than that of said semiconductor substrate, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, said second bias means includes a second semiconductor region of the second conductivity type formed in said first well region and having an impurity concentration higher than that of said first well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region, and said third bias means includes a third semiconductor region of the second conductivity type formed in said second well region and having an impurity concentration higher than that of said second well region, a third potential supplying source, and a third power source line connected between said third potential supplying source and said third semiconductor region.

Claim 7

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; first bias means for biasing said semiconductor substrate by a constant potential; a first well region of a second conductivity type formed in said semiconductor substrate, a digital circuit being formed in said first well region; second bias means for biasing said first well region by a constant potential; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; and third bias means for biasing said second well region by a constant potential, wherein said first bias means includes a first semiconductor region of the first conductivity type formed in that portion of said semiconductor substrate which lies between said first and second well regions and having an impurity concentration higher than that of said semiconductor substrate, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, said second bias means includes a second semiconductor region of the second conductivity type formed in said first well region and having an impurity concentration higher than that of said first well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region, and said third bias means includes a third semiconductor region of the second conductivity type formed in said second well region and having an impurity concentration higher than that of said second well region, a third potential supplying source, and a third power source line connected between said third potential supplying source and said third semiconductor region.

Claim 8

A device according to claim 4, further comprising a fourth semiconductor region of the first conductivity type formed in said first well region and acting as part of an active element; a fourth potential supplying source; a fourth power source line connected between said fourth semiconductor region and said fourth potential supplying source; a fifth semiconductor region of the first conductivity type formed in said second well region and acting as part of an active element; a fifth potential supplying source; a fifth power source line connected between said fifth semiconductor region and said fifth potential supplying source.

Claim 9

A semiconductor integrated circuit device comprising; a semiconductor substrate of a first conductivity type; first bias means for biasing said semiconductor substrate by a constant potential; a first well region of a second conductivity type formed in said semiconductor substrate, a digital circuit being formed in said first well region; second bias means for biasing said first well region by a constant potential; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; third bias means for biasing said second well regions by a constant potential; and a third well region of a first conductivity type formed in said first well region, fourth bias means for biasing said third well region by a constant potential, a fourth well region of the first conductivity type formed in said second well region, and fifth bias means for biasing said fourth well region by a constant potential, wherein said fourth bias means includes a first semiconductor region of the first conductivity type formed in said third well region and having an impurity concentration higher than said third well region, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, and said fifth bias means includes a second semiconductor region of the first conductivity type formed in said fourth well region and having an impurity concentration higher than said fourth well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region.

Claim 10

A semiconductor integrated circuit device comprising; a semiconductor substrate of a first conductivity type; first bias means for biasing said semiconductor substrate by a constant potential; a first well region of a second conductivity type formed in said semiconductor substrate, a digital circuit being formed in said first well region; second bias means for biasing said first well region by a constant potential; a second well region of the second conductivity type which is formed in said semiconductor substrate at a position separated from said first well region and in which an analog circuit comprising complementary metal oxide silicon transistors is formed; third bias means for biasing said second well regions by a constant potential; and a third well region of a first conductivity type formed in said first well region, fourth bias means for biasing said third well region by a constant potential, a fourth well region of the first conductivity type formed in said second well region, and fifth bias means for biasing said fourth well region by a constant potential, wherein said fourth bias means includes a first semiconductor region of the first conductivity type formed in said third well region and having an impurity concentration higher than said third well region, a first potential supplying source, and a first power source line connected between said first potential supplying source and said first semiconductor region, and said fifth bias means includes a second semiconductor region of the first conductivity type formed in said fourth well region and having an impurity concentration higher than said fourth well region, a second potential supplying source, and a second power source line connected between said second potential supplying source and said second semiconductor region.

Claim 11

A device according to claim 6, further comprising a third semiconductor region of the second conductivity type formed in said third well region and acting as part of an active element; a third potential supplying source; a third power source line connected between said third semiconductor region and said third potential supplying source; a fourth semiconductor region of the second conductivity type formed in said fourth well region and acting as part of an active element; a fourth potential supplying source; a fourth power source line connected between said fourth semiconductor region and said fourth potential supplying source.