Apparatus for measuring clock pulse delay in one or more circuits

Claim 2

A clock adjustment circuit for measuring a delay of a measured circuit comprising: a pulse forming circuit for generating a clock pulse, a phase adjusting circuit supplied with said clock pulse at its input terminal, said phase adjusting circuit distributing said supplied clock pulse to a plurality of LSIs in a measured circuit and adjusting the phases of respective LSI clock pulses which are distributed to said LSIs; a selected one of said LSIs operating in response to said distributed clock pulse supplied from said phase adjusting circuit, said LSI executing an operation by providing an output signal responsive to said distributed clock pulse; trigger means for outputting a signal as a trigger out of a rise edge or a fall edge of a signal received from said selected LSI depending on whether or not an inverse logic of said clock pulse is generated when said LSI operation is executed; feedback means for receiving said output signal from said trigger means, and supplying said output signal to an input terminal of said pulse forming circuit; and means for measuring the delay of said measured circuit receiving said distributed clock pulse by measuring an oscillation generated by said clock pulse generated by said pulse forming circuit, and said output signal of said trigger means.

Claim 3

A clock adjustment circuit comprising: a pulse forming circuit; an output of said pulse forming circuit being connected to an input of a measured circuit, and an input of said pulse forming circuit being connected to an output of said measured circuit; said pulse forming circuit comprising: a gate circuit having an input which receives an output from said measured circuit; and a pulse generation circuit for receiving an output from said gate circuit at a first input of said pulse generation circuit, said pulse generation circuit generating a pulse of a predetermined width at a rise or a fall of a trigger signal received at a second input of said pulse generation circuit; said pulse generation circuit further comprising: a first differential circuit for differentiating said trigger signal, said trigger signal being supplied to an input of said first differential circuit; a set-reset flip-flop set at least by an output from either said gate circuit or said first differential circuit, said output of said set-reset flip-flop being the output from said pulse generating circuit; a first delay means responsive to said set-reset flip-flop output for generating an output which is delayed by a predetermined time from said set-reset flip-flop output; and a second differential circuit responsive to said output of said first delay means for differentiating an output from said first delay means and for resetting said set-reset flip-flop; said pulse forming circuit further comprising a frequency counter responsive to said output of said measured circuit for measuring a delay in said measured circuit from a repetition cycle of an oscillation generated when said gate circuit is turned on.

Claim 4

A clock adjustment circuit comprising: a pulse forming circuit; an output of said pulse forming circuit being connected to an input of a measured circuit, and an input of said pulse forming circuit being connected to an output of said measured circuit; said pulse forming circuit comprising: a gate circuit having an input which receives an output from said measured circuit; and a pulse generation circuit for receiving an output from said gate circuit at a first input of said pulse generation circuit, said pulse generation circuit generating a pulse of a predetermined width at a rise or a fall of a trigger signal received at a second input of said pulse generation circuit; said pulse generation circuit further comprising: a first differential circuit for differentiating said trigger signal, said trigger signal being supplied to an input of said first differential circuit; a set-reset flip-flop set at least by an output from either said gate circuit or said first differential circuit, said output of said set-reset flip-flop being the output from said pulse generating circuit; a first delay means responsive to said set-reset flip-flop output for generating an output which is delayed by a predetermined time from said set-reset flip-flop output; and a second differential circuit responsive to said output of said first delay means for differentiating an output from said first delay means and for resetting said set-reset flip-flop; said pulse forming circuit further comprising a frequency counter responsive to said output of said measured circuit for measuring a delay in said measured circuit from a repetition cycle of an oscillation generated when said gate circuit is turned on.

Claim 5

The clock adjustment circuit according to claim 2, wherein said gate circuit further comprises a third differential circuit for differentiating a signal supplied from an output of said measured circuit.

Claim 6

The clock adjustment circuit according to claim 3, wherein said third differential circuit comprises: a delay circuit for inverting an output from said measured circuit, said delay circuit also delaying said output from said measured circuit; and an OR gate receiving at its first input terminal an output from said delay circuit and at its second input terminal an output from said measured circuit, said OR gate providing said third differential circuit output.

Claim 7

The clock adjustment circuit according to claim 2, wherein said first differential circuit comprises: a delay circuit for inverting said trigger signal, said delay circuit also delaying said trigger signal; and a NOR gate receiving at its first input terminal an output from said delay circuit and at its second input terminal said trigger signal, said NOR gate providing said differential circuit output.

Claim 8

The clock adjustment circuit according to claim 3, wherein said third differential circuit comprises at its input terminal an exclusive OR gate, said exclusive OR gate receiving at one of its input terminals a selection signal which is selectively high or low, depending on the logic inversion of the measured circuit.

Claim 9

The clock adjustment circuit according to claim 6, wherein said selection signal causes said third differential circuit to obtain (a) a first delay between rise of a pulse provided to said input of said measured circuit and rise of an output pulse of said measured circuit, said output pulse supplying a high level signal to one input terminal of said exclusive OR gate, or (b) a second delay between a rise of said pulse provided to said input of said measured circuit and a fall of said output pulse of said measured circuit, by supplying a low level signal to said one input terminal of said exclusive OR gate.

Claim 10

The clock adjustment circuit according to claim 7, wherein said third differential circuit comprises means for obtaining the width of an output pulse of said measured circuit based on the difference between said second delay and said first delay.