Chopping type comparator with clocked inverter

Claim 2

A chopping type comparator comprising: a pair of first and second analog switches switchable alternatively with each other between a conductive state and a nonconductive state by a control signal, the first and second analog switches having respective one ends receptive of two input signals to be compared with one another, and respective other ends connected together to form a common junction node; a capacitor having one end coupled to the common junction node of the first and second analog switches; a clocked inverter having at least four FETs and being changeable between an active state and an inactive state by the control signal, one of the FETs being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal connected to another end of the capacitor, the clocked inverter being in the active state when one of the first and second analog switches is switched to the conductive state and being in the inactive state when the other of the first and second switches is in the conductive state; and a third analog switch coupled between the input and output terminals of the clocked inverter and being switchable to a conductive state by the control signal when said one of the first and second analog switches is placed in the conductive state, such that during the inactive state of the clocked inverter a current flow through the clocked inverter is substantially eliminated.

Claim 3

A chopping type comparator comprising: first input means receptive of a first input signal; second input means receptive of a second input signal; control means operative to apply a control signal effective to alternately enable the first and second input means; storage means for storing a third signal produced according to the first and second input signals; a clocked inverter having at least four FETs and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal connected to the storage means, the clocked inverter being in the active state when one of the first and second input means is enabled and being in the inactive state when the other of the first and second input means is enabled; and switch means coupled between the input and output terminals of the clocked inverter so as to receive at its output terminal the third signal and so as to produce at its output terminal a comparison result between the first and second input signals based on the received third signal, such that during the inactive state of the clocked inverter a current flow through the clocked inverter is substantially eliminated.

Claim 4

A chopping type comparator comprising: first input means receptive of a first input signal; second input means receptive of a second input signal; control means operative to apply a control signal effective to alternately enable the first and second input means; storage means for storing a third signal produced according to the first and second input signals; a clocked inverter having at least four FETs and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal connected to the storage means, the clocked inverter being in the active state when one of the first and second input means is enabled and being in the inactive state when the other of the first and second input means is enabled; and switch means coupled between the input and output terminals of the clocked inverter so as to receive at its output terminal the third signal and so as to produce at its output terminal a comparison result between the first and second input signals based on the received third signal, such that during the inactive state of the clocked inverter a current flow through the clocked inverter is substantially eliminated.

Claim 5

A chopping type comparator according to claim 2; wherein the control means includes a second inverter operative in response to the control signal to change the clocked inverter between an active state and an inactive state.

Claim 6

A chopping type comparator according to claim 3; wherein the clocked inverter includes a pair of transistor switches responsive to an output from the second inverter for suppressing a driving current flowing through the clocked inverter in the active state.

Claim 7

A chopping type comparator circuit comprising: a first input switch switchable between a conductive state and a nonconductive state by a control signal; a second input switch switchable between a conductive state and a nonconductive state by a first inverter controlled by the control signal, the second switch being alternatively switched with the first switch from the conductive state to the nonconductive state, the first and second switches having respective one ends receptive of two input signals to be compared with each other, and respective other ends coupled to form a common junction node; a capacitor having one end coupled to the common junction node of the first and second switches; a clocked inverter having at least four FETS and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal coupled to another end of the capacitor, the clocked inverter being in the active state when one of the first and second switches is switched to the conductive state and being in the inactive state when the other of the first and second switches is in the conductive state; and a third switch coupled between the input and output terminals of the clocked inverter and being switchable to a conductive state by the control signal when the one of the first and second switches is switched to the conductive state, such that during the inactive state of the clocked inverter a current flow through the clocked inverter is substantially eliminated.

Claim 8

A chopping type comparator circuit comprising: a first input switch switchable between a conductive state and a nonconductive state by a control signal; a second input switch switchable between a conductive state and a nonconductive state by a first inverter controlled by the control signal, the second switch being alternatively switched with the first switch from the conductive state to the nonconductive state, the first and second switches having respective one ends receptive of two input signals to be compared with each other, and respective other ends coupled to form a common junction node; a capacitor having one end coupled to the common junction node of the first and second switches; a clocked inverter having at least four FETS and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal coupled to another end of the capacitor, the clocked inverter being in the active state when one of the first and second switches is switched to the conductive state and being in the inactive state when the other of the first and second switches is in the conductive state; and a third switch coupled between the input and output terminals of the clocked inverter and being switchable to a conductive state by the control signal when the one of the first and second switches is switched to the conductive state, such that during the inactive state of the clocked inverter a current flow through the clocked inverter is substantially eliminated.

Claim 9

An Analog to Digital converting circuit, comprising: a plurality of chopping type comparator circuits; wherein each of the plurality of chopping type comparator circuits include: a first input switch switchable between a conductive state and a nonconductive state by a control signal; a second input switch switchable between a conductive state and a nonconductive state by a first inverter controlled by the control signal, the second switch being alternatively switched with the first switch from the conductive state to the nonconductive state, the first and second switches having respective one ends receptive of two input signals to be compared with each other, and respective other ends coupled to form a common junction node; a capacitor having one end coupled to the common junction node of the first and second switches; a clocked inverter having at least four FETS and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal coupled to another end of the capacitor, the clocked inverter being in the active state when one of the first and second switches is switched to the conductive state and being in the inactive state when the other of the first and second switches is in the conductive state; and a third switch coupled between the input and output terminals of the clocked inverter and being switchable to a conductive state by the control signal when the one of the first and second switches is switched to the conductive state.

Claim 10

An Analog to Digital converting circuit, comprising: a plurality of chopping type comparator circuits; wherein each of the plurality of chopping type comparator circuits include: a first input switch switchable between a conductive state and a nonconductive state by a control signal; a second input switch switchable between a conductive state and a nonconductive state by a first inverter controlled by the control signal, the second switch being alternatively switched with the first switch from the conductive state to the nonconductive state, the first and second switches having respective one ends receptive of two input signals to be compared with each other, and respective other ends coupled to form a common junction node; a capacitor having one end coupled to the common junction node of the first and second switches; a clocked inverter having at least four FETS and being changeable between an active state and an inactive state by the control signal, one of the FETS being switchable between a conductive state and a nonconductive state by the control signal and a second of the FETS concurrently switching with said one of the FETS between the conductive state and the nonconductive state by the control signal, the clocked inverter having an output terminal and an input terminal coupled to another end of the capacitor, the clocked inverter being in the active state when one of the first and second switches is switched to the conductive state and being in the inactive state when the other of the first and second switches is in the conductive state; and a third switch coupled between the input and output terminals of the clocked inverter and being switchable to a conductive state by the control signal when the one of the first and second switches is switched to the conductive state.