Presettable dynamic delay flip-flop circuit

Claim 2

A presettable dynamic delay flip-flop circuit which comprises gate means for stopping transfer of a clock pulse at least during a data-presetting period and permitting transfer of a clock pulse on other occasions than during the data-presetting period; first delay means remaining intact during the data-presetting period and carrying out 1/2 bit delay in synchronism with a first output gate signal from the gate means on other occasions than during the data-presetting period; second delay means connected to the output terminal of the first delay means, and served to feedback a delayed out signal from the first delay means, be rendered conducting during the data-presetting period and carry out 1/2 bit delay in synchronism with a second output gate signal from the gate means on other occasions than during the data-presetting period; and switching means designed to be rendered conducting only during the data-presetting period and supply preset data to the second delay means.

Claim 3

The presettable dynamic delay flip-flop circuit according to claim 1, wherein the gate means comprises a NOR gate for sending forth a first gate signal when supplied with a preset-enable signal and a clock pulse; and an inverter for inverting the logic level of an output signal from the NOR gate and issuing a second gate signal.

Claim 4

The presettable dynamic delay flip-flop circuit according to claim 1, wherein the first delay means, second delay means and switching means respectively comprise a clocked inverter including a complementary type inverter circuit formed of a pair of field effect transistors, and transfer gate field effect transistors provided on the source sides of said paired field effect transistors and rendered conducting when supplied with inputs of opposite polarities; and when the transfer gate is rendered conducting, an input signal supplied to the inverter circuit is drawn out with the logic level inverted.

Claim 5

The presettable dynamic delay flip-flop circuit according to claim 1, wherein the first delay means, second delay means and switching means respectively comprise an inverter for inverting the logic level of an input signal supplied thereto; and a transfer gate for transferring an output signal from the inverter, said transfer gate being formed of a pair of opposite polarities whose drains and sources are respectively connected together and are rendered conducting when the respective gates are supplied with input signals whose phases are inverted from each other.

Claim 6

The presettable dynamic delay flip-flop circuit according to claim 1, wherein the first delay means, second delay means and switching means respectively comprise an inverter formed of a first depletion type field effect transistor whose gate and source are short-circuited and a second enhancement type field effect transistor having the same conductivity type as the first depletion type field effect transistor and connected in series thereto, thereby inverting the logic level of an input signal supplied to the gate of the second enhancement type field effect transistor; and a third field effect transistor having the same conductivity type as the first and second field effect transistors and designed to be rendered conducting when the gate of said third field effect transistor is supplied with a prescribed signal, thereby transferring an output signal from said inverter.

Claim 7

The presettable dynamic delay flip-flop circuit according to claim 1, which further comprises an inverter for inverting the logic level of an output signal from the second delay means, and wherein an output from the second delay means is drawn out as a first output signal from the flip-flop circuit, and an output from the inverter is drawn out as a second output signal from said flip-flop circuit.

Claim 8

A programmable counter which comprises a prescribed number of presettable dynamic delay flip-flop circuits collectively arranged in the ripple carrier type, each of said flip-flop circuits including gate means for stopping transfer of a clock pulse at least during a period in which a program is to be executed and permitting transfer of a clock pulse on other occasions than during the programexecuting period, first delay means served to remain intact during the program-executing period and carry out 1/2 bit delay in synchronism with a first output gate signal from the gate means on other occasions than during the programexecuting period, second delay means connected to the output terminal of the first delay means and served to feedback a delayed output signal from the first delay means, be rendered conducting during the program-executing period and carry out 1/2 bit delay in synchronism with a second output gate signal from the gate means on other occasions than during the program-executing period, and switching means rendered conducting only during the program-executing period to supply program data to the second delay means; a NAND gate for NANDing a prescribed output from each of the plural flip-flop circuits; third delay means for carrying out a prescribed delaying operation in synchronism with a clock pulse when supplied with an output from the NAND gate, said third delay means including a first clocked inverter operated by a clock pulse whose logic level has been inverted and a second clocked inverter connected in series to the first clocked inverter to be operated by a clock pulse whose logic level has been inverted; and inverter means for inverting the logic level of an output signal from the third delay means to send forth a program-enable signal.

Claim 9

A programmable counter which comprises a prescribed number of presettable dynamic delay flip-flop circuits collectively arranged in the ripple carrier type, each of said flip-flop circuits including gate means for stopping transfer of a clock pulse at least during a period in which a program is to be executed and permitting transfer of a clock pulse on other occasions than during the programexecuting period, first delay means served to remain intact during the program-executing period and carry out 1/2 bit delay in synchronism with a first output gate signal from the gate means on other occasions than during the programexecuting period, second delay means connected to the output terminal of the first delay means and served to feedback a delayed output signal from the first delay means, be rendered conducting during the program-executing period and carry out 1/2 bit delay in synchronism with a second output gate signal from the gate means on other occasions than during the program-executing period, and switching means rendered conducting only during the program-executing period to supply program data to the second delay means; a NAND gate for NANDing a prescribed output from each of the plural flip-flop circuits; third delay means for carrying out a prescribed delaying operation in synchronism with a clock pulse when supplied with an output from the NAND gate, said third delay means including a first clocked inverter operated by a clock pulse whose logic level has been inverted and a second clocked inverter connected in series to the first clocked inverter to be operated by a clock pulse whose logic level has been inverted; and inverter means for inverting the logic level of an output signal from the third delay means to send forth a program-enable signal.