Voltage comparator having capacitively cascade-connected inverting amplifiers

Claim 2

A comparator for comparing a first input voltage signal with a second input voltage signal to provide at an output thereof an output voltage signal of a logic level 1 or 0 depending on the relationship between magnitudes of the first and second input voltage signals comprising: a plurality of capacitively cascade-connected inverting amplifier stages each having an MOS inverter and an input-coupling capacitive element connected to an input of said inverter; input circuit means for alternately coupling the first and second input voltage signals to be compared to the input-coupling capacitive element of the first inverting amplifier stage; a bias circuit including first and second MOS transistors having their source-drain paths connected in series across a power source, each of said first and second MOS transistors having its gate electrode connected to its drain electrode, and a third MOS transistor having its source-drain path connected in parallel with that of said second MOS transistor and its gate electrode connected to receive a control voltage; and switching means for coupling the junction of said series-connected first and second MOS transistors to the input of said inverter of each of said cascade-connected inverting amplifier stages at a predetermined time interval.

Claim 3

A comparator for comparing a first input voltage signal with a second input voltage signal to provide at an output thereof an output voltage signal of a logic level 1 or 0 depending on the relationship between magnitudes of the first and second input voltage signals comprising: a plurality of capacitively cascade-connected inverting amplifier stages each having an MOS inverter and an input-coupling capacitive element connected to an input of said MOS inverter; input circuit means for alternately coupling the first and second input voltage signals to be compared to said input-coupling capacitive element of a first stage of said cascade-connected inverting amplifier stages; bias circuit means for producing a bias voltage at its output; and switching means for coupling the bias voltage of said bias circuit means to the input of said inverter of each of said cascade-connected inverting amplifier stages at a predetermined time interval; said bias circuit means including first and second MOS transistors having their source-drain paths connected in series across a power source with the junction of said series-connected first and second MOS transistors connected to said output of said bias circuit, each of said first and second MOS transistors having its gate electrode connected to its drain electrode; a third MOS transistor having its source-drain path connected in parallel with that of said second MOS transistor; a monitoring MOS inverter having its input connected to said output of said bias circuit, said monitoring MOS inverter having substantially the same transfer characteristic as that of said inverter of each of said cascade-connected inverting amplifier stages; and control circuit means responsive to an output voltage of said monitoring inverter to apply a control voltage to a gate electrode of said third MOS transistor to thereby control the bias voltage of said bias circuit.

Claim 4

A comparator for comparing a first input voltage signal with a second input voltage signal to provide at an output thereof an output voltage signal of a logic level 1 or 0 depending on the relationship between magnitudes of the first and second input voltage signals comprising: a plurality of capacitively cascade-connected inverting amplifier stages each having an MOS inverter and an input-coupling capacitive element connected to an input of said MOS inverter; input circuit means for alternately coupling the first and second input voltage signals to be compared to said input-coupling capacitive element of a first stage of said cascade-connected inverting amplifier stages; bias circuit means for producing a bias voltage at its output; and switching means for coupling the bias voltage of said bias circuit means to the input of said inverter of each of said cascade-connected inverting amplifier stages at a predetermined time interval; said bias circuit means including first and second MOS transistors having their source-drain paths connected in series across a power source with the junction of said series-connected first and second MOS transistors connected to said output of said bias circuit, each of said first and second MOS transistors having its gate electrode connected to its drain electrode; a third MOS transistor having its source-drain path connected in parallel with that of said second MOS transistor; a monitoring MOS inverter having its input connected to said output of said bias circuit, said monitoring MOS inverter having substantially the same transfer characteristic as that of said inverter of each of said cascade-connected inverting amplifier stages; and control circuit means responsive to an output voltage of said monitoring inverter to apply a control voltage to a gate electrode of said third MOS transistor to thereby control the bias voltage of said bias circuit.

Claim 5

A comparator according to claim 2 wherein said control circuit means comprises a first voltage divider for producing a reference voltage; a differential amplifier for producing an output voltage proportional to the difference between the reference voltage of said first voltage divider and the output voltage of said monitoring inverter; an integrator circuit connected to an output of said integrator circuit; and a second voltage divider having its output connected to the gate electrode of said third transistor and to an output of said integrator circuit.

Claim 6

A comparator according to claim 2 wherein said inverters of said cascade-connected inverting amplifier stages and said monitoring inverter each have a depletion type load MOS transistor and an enhancement type driver MOS transistor, and said first MOS transistor of said bias circuit is of depletion type and said second and third MOS transistors of said bias circuit are of enhancement type.