High accuracy MOS comparator

Claim 2

A voltage comparator comprising a differencing circuit for producing a difference signal indicating the polarity of the difference between two input signals, an amplifier having an input node for receiving said difference signal and an output node for manifesting an amplified signal, first switching means effective when placed in a first state to establish a biasing connection for setting said amplifier at a predetermined operating point which will be maintained after such connection is interrupted and effective when placed in a second state to interrupt such connection, leaving said amplifier biased at said operating point, output circuitry for receiving signals manifested at the output node of said amplifier, said output circuitry including at least one stage which can be set to a first condition wherein it is incapable of responding to any signal manifested at said amplifier output node and settable thereafter to an alternative condition in which it is responsive to such a signal, second switching means effective when placed in a first state to set said output stage in said first condition thereof and effective when placed in a second state to set said output stage in an alternative condition wherein it responds to the amplifier output signal, and control means for causing said first switching means and said second switching means to operate in a timed relationship such that said second switching means is in its first state at the time when said fist switching means changes from its first state to its second state, whereby said output stage assumes its first condition during the time when a transient signal is being generated by interruption of the biasing connection in such amplifier and thereafter assumes an alternative condition responsive to the amplified difference signal at a time when said transient signal does not exist.

Claim 3

A voltage comparator as defined in claim 1 wherein said differencing circuit comprises a pair of passive MOS capacitors each having an electrode connected to a common output node and having another electrode connected to a respective one of two input nodes to which said input signals respectively are applied, and switching devices for conditioning said capacitors so that the difference signal manifested at said common output node has a polarity which denotes the relative magnitudes of said input signals.

Claim 4

A voltage comparator as defined by claim 1 wherein said amplifier includes an FET having a gate to which the difference signal produced by said differencing circuit is applied and a drain at which an amplified signal can be manifested, said switching means being effective in its first state to interconnect said gate and drain and being effective in its second state to interrupt such connection.

Claim 5

A voltage comparator as defined by claim 1 wherein said one stage of said output circuitry comprises an FET latching circuit capable of assuming an initial neutral condition wherein it is unresponsive to signals received from said amplifier and capable of switching from said initial condition to a second condition wherein it can assume either of two alternative final states in response to the polarity of a signal received from said amplifier.

Claim 6

A voltage comparator comprising a differencing circuit for producing a difference signal indicating the polarity of the difference between two input signals, a first amplifier having an input node for receiving said difference signal and an output node for manifesting an amplified signal, first switching means effective when placed in a first state to establish a biasing connection for setting said first amplifier at a predetermined operating point which will be maintained after such connection is interrupted and effective when placed in a second state to interrupt such connection, leaving said amplifier biased at said operating point, a buffer amplifier having an input node for receiving a signal manifested at the output node of said first amplifier and having an output node for manifesting an amplified signal, second switching means effective when placed in a first state to establish a biasing connection for setting said buffer amplifier at a predetermined operating point which will be maintained after such connection is interrupted and effective when placed in a second state to interrupt such connection, said buffer amplifier being unresponsive to signals received at its input node while said switching means is in its first state, a latching circuit for receiving signals manifested at the output node of said buffer amplifier, said latching circuit being capable of assuming an initial neutral condition wherein it is unresponsive to signals received from said buffer amplifier and capable of switching from said initial condition to a second condition in which it can assume either of two alternative final states in accordance with the polarity of the signal received from said buffer amplifier, third switching means effective when placed in a first state to place said latching circuit in its initial neutral condition and effective when placed in a second state to set said latching circuit to its second condition wherein it assumes one of its alternative final states according to said amplified signal polarity, and control means for causing said first, second and third switching means to operate in a timed relationship such that said second switching means is in its first state when said first switching means changes from its first state to its second state, and said third switching means is in its first state when said second switching means changes from its first state to its second state, whereby any transient signal which is generated by interruption of the biasing connection to said first amplifier is absorbed in said buffer amplifier, and any transient signal which is generated by interruption of the biasing connection to said buffer amplifier is absorbed in said latching circuit, thus insuring that the final state of said latching circuit is determined by the polarity of said difference signal independently of said transient signals.

Claim 7

A voltage comparator comprising a differencing circuit for producing a difference signal indicating the polarity of the difference between two input signals, a first amplifier having an input node for receiving said difference signal and an output node for manifesting an amplified signal, first switching means effective when placed in a first state to establish a biasing connection for setting said first amplifier at a predetermined operating point which will be maintained after such connection is interrupted and effective when placed in a second state to interrupt such connection, leaving said amplifier biased at said operating point, a buffer amplifier having an input node for receiving a signal manifested at the output node of said first amplifier and having an output node for manifesting an amplified signal, second switching means effective when placed in a first state to establish a biasing connection for setting said buffer amplifier at a predetermined operating point which will be maintained after such connection is interrupted and effective when placed in a second state to interrupt such connection, said buffer amplifier being unresponsive to signals received at its input node while said switching means is in its first state, a latching circuit for receiving signals manifested at the output node of said buffer amplifier, said latching circuit being capable of assuming an initial neutral condition wherein it is unresponsive to signals received from said buffer amplifier and capable of switching from said initial condition to a second condition in which it can assume either of two alternative final states in accordance with the polarity of the signal received from said buffer amplifier, third switching means effective when placed in a first state to place said latching circuit in its initial neutral condition and effective when placed in a second state to set said latching circuit to its second condition wherein it assumes one of its alternative final states according to said amplified signal polarity, and control means for causing said first, second and third switching means to operate in a timed relationship such that said second switching means is in its first state when said first switching means changes from its first state to its second state, and said third switching means is in its first state when said second switching means changes from its first state to its second state, whereby any transient signal which is generated by interruption of the biasing connection to said first amplifier is absorbed in said buffer amplifier, and any transient signal which is generated by interruption of the biasing connection to said buffer amplifier is absorbed in said latching circuit, thus insuring that the final state of said latching circuit is determined by the polarity of said difference signal independently of said transient signals.

Claim 8

A voltage comparator as defined by claim 5 wherein said differencing circuit comprises: a pair of passive MOS capacitors each having an electrode connected to a common output node and having another electrode connected to a respective one of two input nodes to which said input signals respectively are applied, and switching devices for conditioning said capacitors so that the difference signal manifested at said common output nodes has a polarity which denotes the relative magnitudes of said input signals.

Claim 9

A voltage comparator as defined by claim 5 wherein each of said amplifiers includes an FET having a gate connected to said input node and a drain at which an amplified signal can be manifested, each of said first and second switching means being effective in its first state to interconnect the gate and drain of its respective amplifier FET and being effective in its second state to interrupt said connection.

Claim 10

A voltage comparator as defined by claim 5 wherein said latching circuit includes the following elements: an input node coupled to the output node of said buffer amplifier, first and second output nodes between which there can be manifested, whenever said latching circuit is in one of its alternative final states, an amplified output voltage whose polarity represents the final state of said latching circuit, thereby denoting the relative magnitude of the original input voltages applied to said differencing circuit, first and second FETs each having source, gate and drain electrodes, the source of said first FET being connected to said input node, first and second capacitors, means providing a common connection among said first capacitor, the gate of said first FET, the drain of said second FET and the second of said output nodes, and means providing a common connection among said second capacitor, the gate of said second FET, the drain of said first FET and the first of said output nodes, said third switching means being effective in its first state to place said first and second output nodes at substantially the same potential for concurrently charging said capacitors to a predetermined level and being effective in its second state to permit the development of an output voltage between said output nodes by the selective discharge of said first or second capacitor through said second or first FET, respectively, according to the polarity of the signal furnished by said buffer amplifier to said latching circuit.