Dual port semiconductor memory device with high speed data transfer during reading and writing modes

Claim 2

A semiconductor memory device comprising: a first memory array having a plurality of first memory cells arranged in a plurality of columns, a second memory array for temporarily storing a read out data signal from said first memory array and write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns, wherein each of said second memory cells includes first and second complementary storage nodes, bidirectional inverting means interconnecting said first and second storage nodes; means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction, data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal, read out means for reading out a data signal from one of said plurality of first memory cells, amplifying means for reading and amplifying both a data signal read out by said read out means and a data signal temporarily stored in each second memory cell, first connecting means for electrically connecting one node of said complementary storage nodes to said amplifying means at the time of data reading and data writing, second connecting means, for electrically connecting the other one of said complementary storage nodes to said data bus means, after said one node is electrically connected to said amplifying means by said first connecting means, at the time of said data reading, and third connecting means for electrically connecting said one node to said data bus means, before said one node is electrically connected to said amplifying means by said first connecting means, at the time of said data writing.

Claim 3

A semiconductor memory device comprising: a first memory array having a plurality of first memory cells arranged in a plurality of columns, a second memory array for temporarily storing a readout data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns, wherein each second memory cell includes a first node, a second node, first inverting means for inverting the potential of said first node to provide the same to said second node, second inverting means for inverting the potential of said second node to provide the same to said first node, the drive capability of said first inverting means being greater than that of said second inverting means, data bus means for receiving both a data signal readout from said second memory cell and an externally applied data signal, readout means for reading out a data signal from one of said plurality of first memory cells, amplifying means for sensing and amplifying both a data signal readout by said readout means and a data signal temporarily stored in said each second memory cell, first connecting means for electrically connecting each first node to said amplifying means at the time of data reading and data writing, second connecting means for electrically connecting and disconnecting said each second node to and from said data bus means during data reading and data writing, respectively, third connecting means for electrically connecting and disconnecting said each first node to and from said data bus means during data writing and data reading respectively, and first and second control signal generating means generating control signals for controlling said second and third connecting means, said first control signal generating means generating a first control signal for controlling the second connecting means to connect the second node to said data bus means during data reading and to isolate the second node from said data bus during data writing, said second control signal generating means generating a second control signal for controlling the third connecting means to connect the first node to said data bus means during data writing and to isolate the first node from said data bus means during data reading.

Claim 4

A semiconductor memory device comprising: a first memory array having a plurality of first memory cells arranged in a plurality of columns, a second memory array for temporarily storing a readout data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns, wherein each second memory cell includes a first node, a second node, first inverting means for inverting the potential of said first node to provide the same to said second node, second inverting means for inverting the potential of said second node to provide the same to said first node, the drive capability of said first inverting means being greater than that of said second inverting means, data bus means for receiving both a data signal readout from said second memory cell and an externally applied data signal, readout means for reading out a data signal from one of said plurality of first memory cells, amplifying means for sensing and amplifying both a data signal readout by said readout means and a data signal temporarily stored in said each second memory cell, first connecting means for electrically connecting each first node to said amplifying means at the time of data reading and data writing, second connecting means for electrically connecting and disconnecting said each second node to and from said data bus means during data reading and data writing, respectively, third connecting means for electrically connecting and disconnecting said each first node to and from said data bus means during data writing and data reading respectively, and first and second control signal generating means generating control signals for controlling said second and third connecting means, said first control signal generating means generating a first control signal for controlling the second connecting means to connect the second node to said data bus means during data reading and to isolate the second node from said data bus during data writing, said second control signal generating means generating a second control signal for controlling the third connecting means to connect the first node to said data bus means during data writing and to isolate the first node from said data bus means during data reading.

Claim 5

The semiconductor device according to claim 2, wherein said first inverting means comprises first and second field effect semiconductor elements having complementary polarities connected in series between a high potential power supply and a low potential power supply, said second inverting means comprises third and fourth field effect semiconductor elements connected in series between said high potential power supply and said low potential power supply, and having a polarity identical to that of said first field effect semiconductor element and a polarity identical to that of said second field effect semiconductor element, respectively, the drive capability of said first field effect semiconductor element is greater than that of said third field effect semiconductor element, the size of said second field effect semiconductor element is larger than that of said fourth field effect semiconductor element.

Claim 6

The semiconductor memory device according to claim 2, wherein said first inverting means comprises a plurality of inverters connected between said first node and said second node in parallel to each other, and said second inverting means comprises a single inverter connected between said first node and said second node in anti-parallel to said plurality of inverters.

Claim 7

The semiconductor memory device according to claim 2, wherein said first memory array further comprises first and second bit lines provided corresponding to each of said plurality of columns, said data signal stored in each first memory cell is read out by said readout means to said first and second bit lines corresponding to said columns in which it is arranged, said amplifying means comprises a plurality of differential amplifying means provided corresponding to said plurality of columns.

Claim 8

The semiconductor memory device according to claim 5, wherein each of said plurality of differential amplifying means comprises first and second signal lines, fifth and sixth field effect semiconductor elements of complementary polarity, provided between said first signal line and the corresponding said first bit line, and between said second signal line and the corresponding said first bit line, respectively, and controlled according to the potential of the corresponding said second bit line, seventh and eight field effect semiconductor elements of complementary polarity, provided between the corresponding said second bit line and said first signal line and between the corresponding said second bit line and said second signal line, respectively, and controlled according to the potential of the corresponding said first bit line, the polarity of said seventh field effect semiconductor element is identical to that of said fifth field effect semiconductor element, the polarity of said eight field effect semiconductor element is identical to that of said sixth field effect semiconductor element, said first and second signal lines are applied with a high potential and a low potential, respectively, after said first node and said amplifying means are electrically connected by said first connecting means, at the time of said data writing, said first and second signal lines are applied with said high potential and said low potential, respectively, before said first node is electrically connected to said amplifying means, at the time of said data reading.

Claim 9

The semiconductor memory device according to claim 6, wherein said first connecting means comprises a plurality of ninth field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of ninth field effect semiconductor elements are connected between the corresponding said differential amplifying means and said first node of the corresponding said second memory cell, and controlled to conduct only at the time of said data writing and said data reading.

Claim 10

The semiconductor memory device according to claim 7, wherein said second connecting means comprises a plurality of tenth field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of tenth field effect semiconductor elements is provided between said second node of the corresponding said second memory cell and said data bus means, and controlled to conduct after the corresponding said ninth field effect semiconductor elements is conductive, at the time of said data reading.

Claim 11

The semiconductor memory device according to claim 8, wherein said third connecting means comprises a plurality of eleventh field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of eleventh field effect semiconductor elements is provided between said first node of the corresponding said second memory cell and said data bus means, and controlled to conduct before the corresponding said ninth field effect semiconductor element is conductive, at the time of said data writing.

Claim 12

The semiconductor memory device according to claim 7, wherein said third connecting means comprises a plurality of eleventh field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of eleventh field effect semiconductor elements is provided between said first node of the corresponding said second memory cell and said data bus means, and controlled to conduct before the corresponding said ninth field effect semiconductor element is conductive, at the time of said data writing.

Claim 13

The semiconductor memory device according to claim 7, wherein said plurality of ninth field effect semiconductor elements conduct simultaneously.

Claim 14

The semiconductor memory device according to claim 8, wherein each of said plurality of tenth field effect semiconductor elements conducts sequentially over time.

Claim 15

The semiconductor memory device according to claim 9, wherein each of said plurality of eleventh field effect semiconductor elements conducts sequentially over time.

Claim 16

The semiconductor memory device according to claim 10, wherein each of said plurality of eleventh field effect semiconductor elements conducts sequentially over time.

Claim 17

The semiconductor memory device according to claim 1, wherein said data bus means comprises a single signal line.

Claim 18

The semiconductor memory device according to claim 2, wherein said data bus means comprises a single signal line.

Claim 19

The semiconductor memory device according to claim 9, wherein said data bus means comprises a single signal line.

Claim 20

The semiconductor memory device according to claim 1, wherein said plurality of first memory cells are arranged also in a plurality of rows in said first memory array, said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows, each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply, each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

Claim 21

The semiconductor memory device according to claim 2, wherein said plurality of first memory cells are arranged also in a plurality of rows in said first memory array, said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows, each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply, each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

Claim 22

The semiconductor memory device according to claim 17, wherein said plurality of first memory cells are arranged also in a plurality of rows in said first memory array, said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows, each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply, each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

Claim 25

A semiconductor memory device comprising: a first memory array having a plurality of first memory cells arranged in a plurality of columns; a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns, wherein each of said second memory cells includes first and second complementary storage nodes, bidirectional inverting means interconnecting said first and second storage nodes, means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction, data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal, read out means for reading out a data signal from one of said plurality of first memory cells, sense amplifier means for sensing and amplifying a data signal read out by said read out means and a data signal temporarily stored in each second memory cell, first connecting means for electrically connecting one node of said complementary storage nodes to said sense amplifier means at the time of data reading and data writing, second connecting means, for electrically connecting and disconnecting the other one of said complementary storage nodes to and from said data bus means during data reading and data writing, respectively, third connecting means for electrically connecting and disconnecting said one node to and from said data bus means during data writing and data reading, respectively, first and second control signal generating means for generating control signals for controlling said second and third connecting means, said first control signal generating means generating a first control signal for controlling the second connecting means to connect said other node to said data bus means during data reading and to isolate said other node from said data bus during data writing, said second control signal generating means generating a second control signal for controlling the third connecting means to connect said one node to said data bus means during data writing and to isolate said one node from said data bus means during data reading.

Claim 26

A semiconductor memory device comprising: a first memory array having a plurality of first memory cells arranged in a plurality of columns; a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns, wherein each of said second memory cells includes first and second complementary storage nodes, bidirectional inverting means interconnecting said first and second storage nodes, means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction, data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal, read out means for reading out a data signal from one of said plurality of first memory cells, sense amplifier means for sensing and amplifying a data signal read out by said read out means and a data signal temporarily stored in each second memory cell, first connecting means for electrically connecting one node of said complementary storage nodes to said sense amplifier means at the time of data reading and data writing, second connecting means, for electrically connecting and disconnecting the other one of said complementary storage nodes to and from said data bus means during data reading and data writing, respectively, third connecting means for electrically connecting and disconnecting said one node to and from said data bus means during data writing and data reading, respectively, first and second control signal generating means for generating control signals for controlling said second and third connecting means, said first control signal generating means generating a first control signal for controlling the second connecting means to connect said other node to said data bus means during data reading and to isolate said other node from said data bus during data writing, said second control signal generating means generating a second control signal for controlling the third connecting means to connect said one node to said data bus means during data writing and to isolate said one node from said data bus means during data reading.