Semiconductor memory including an output latch having hysteresis characteristics

Claim 2

A semiconductor memory device comprising: a plurality of memory cells each storing information; means for selecting a memory cell out of said plurality of memory cells in response to an externally applied address signal; sense amplifier means for amplifying data stored in said selected memory cell; output buffer means for providing data amplified by said sense amplifier means to a device external to said memory device; a data bus for connecting said sense amplifier means to said output buffer means; precharge means responsive to a change in said external address signal for holding said data bus at an intermediate potential level between high and low potential levels for a predetermined period, and hysteresis latch means connected between said data bus said output buffer means, said hysteresis latch means having hysteresis in an input/output characteristic thereof and having first and second input switching levels for defining an output level thereof, said first switching level being higher than said intermediate level and lower than said high level, said second switching level being lower than said intermediate level and higher than said low level, wherein hysteresis latch means latches data on said data bus that is sent out in an immediately preceding cycle during the time when said data bus is held at said intermediate level.

Claim 3

A semiconductor memory device in accordance with claim 1, wherein said plurality of memory cells are divided into a plurality of blocks, each of said plurality of blocks comprising a sense amplifier responsive to said external address signal for detecting and amplifying information stored in the selected memory cell and a switching circuit for selectively outputting an output of a corresponding one of said sense amplifiers to said data bus responsive to said external address signal.

Claim 4

A semiconductor memory device in accordance with claim 1, wherein said hysteresis latch means comprises a Schmidt trigger circuit.

Claim 5

A semiconductor memory device in accordance with claim 3, wherein said Schmidt trigger circuit comprises: a resistive element having first and second terminals, said first terminal connected to an input terminal of said Schmidt trigger circuit, a first inverter having an input terminal connected to the second terminal of said resistive element and an output terminal connected to an output terminal of said Schmidt trigger circuit, and a second inverter having an input terminal connected to the output terminal of said first inverter and an output terminal connected to the second terminal of said resistive element and the input terminal of said first inverter.

Claim 6

A semiconductor memory device in accordance with claim 4, wherein said first and second inverters each comprises a CMOS inverter in which a p channel field effect transistor and an n channel field effect transistor are connected in series and have commonly connected gates.

Claim 7

A semiconductor memory device comprising: a data bus; a plurality of memory cells for storing information; means for selecting a memory cell out of said plurality of memory cells in response to an externally applied address signal; said plurality of memory cells being divided into a plurality of blocks, each of said plurality of blocks comprising a sense amplifier responsive to said external address signal for detecting and amplifying information stored in a selected memory cell and a switching circuit for selectively outputting an output of a corresponding one of said sense amplifiers to said data bus responsive to said externally applied address signal; precharge means responsive to a change in said external address signal for holding said data bus at an intermediate potential level between high and low potential levels for a predetermined period; output buffer means for outputting data from said selected memory cell; and hysteresis latch means connected between said data bus and said output buffer means, said hysteresis latch means having hysteresis in an input-output characteristic thereof and having first and second input switching levels for defining an output level thereof, said first switching level being higher than said intermediate level and lower than said high level, said second switching level being lower than said intermediate level and higher than said low level, wherein said hysteresis latch means latches data on said data bus that is sent out in an immediately preceding cycle during the time when said data bus is held at said intermediate level.

Claim 8

A semiconductor memory device comprising: a data bus; a plurality of memory cells for storing information; means for selecting a memory cell out of said plurality of memory cells in response to an externally applied address signal; said plurality of memory cells being divided into a plurality of blocks, each of said plurality of blocks comprising a sense amplifier responsive to said external address signal for detecting and amplifying information stored in a selected memory cell and a switching circuit for selectively outputting an output of a corresponding one of said sense amplifiers to said data bus responsive to said externally applied address signal; precharge means responsive to a change in said external address signal for holding said data bus at an intermediate potential level between high and low potential levels for a predetermined period; output buffer means for outputting data from said selected memory cell; and hysteresis latch means connected between said data bus and said output buffer means, said hysteresis latch means having hysteresis in an input-output characteristic thereof and having first and second input switching levels for defining an output level thereof, said first switching level being higher than said intermediate level and lower than said high level, said second switching level being lower than said intermediate level and higher than said low level, wherein said hysteresis latch means latches data on said data bus that is sent out in an immediately preceding cycle during the time when said data bus is held at said intermediate level.