Memory input buffer with hysteresis

Claim 2

An input circuit for receiving an input signal and providing an output signal in response thereto, comprising: a first transistor of a first conductivity type having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a switch point control node, and a control electrode for receiving the input signal; a second transistor of a second conductivity type having a first current electrode coupled to a second power supply terminal, a second current electrode coupled to the switch point control node, and a control electrode for receiving the input signal; an inverter having an input coupled to the switch point control node, and an output; load means and a third transistor of the first conductivity type coupled in series between the first power supply terminal and the switch point control node, the third transistor having a control electrode coupled to the output of the inverter and the load means for limiting current through the third transistor; and output means, coupled to the inverter, for providing the output signal.

Claim 3

The input buffer of claim 1 wherein: the third transistor has a first current electrode coupled to the switch point control node, and a second current electrode; and the load means is coupled between the first power supply terminal and the second current electrode of the third transistor.

Claim 4

The input buffer of claim 2 wherein the first and third transistors are P channel transistors and the second transistor is an N channel transistor.

Claim 5

The input buffer of claim 3 wherein the load means is a fourth transistor of the first conductivity type having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the second current electrode of the third transistor, and a control electrode coupled to the second power supply terminal.

Claim 6

The input buffer of claim 4 further comprising: a fourth transistor of the first conductivity type interposed between the first current electrode of the third transistor and the first power supply terminal, the fourth transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to first current electrode of the third transistor, and a control electrode for receiving a control signal; and a fifth transistor of the second conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the switch point control node, and a control electrode for receiving the control signal.

Claim 7

The input buffer of claim 1 wherein the load means is a fourth transistor of the first conductivity type.

Claim 8

The input buffer of claim 6 wherein the third and fourth transistors are coupled in series between the first power supply terminal and the switch point control node, said fourth transistor having a control electrode coupled to the second power supply terminal.

Claim 9

The input buffer of claim 7 wherein: the fourth transistor has a first current electrode coupled to the first power supply terminal, and a second current electrode; the third transistor has a first current electrode coupled to the second current electrode of the fourth transistor, and a second current electrode coupled to the switch point control node.

Claim 10

A memory, comprising: a plurality of memory cells located at intersections of word lines and bit lines; a row decoder, coupled to the word lines, for enabling a selected word line as determined by a row address comprised of a plurality of row address signals at first or second logic states; equalization means, coupled to the bit lines, for equalizing the voltages on the bit lines in response to receiving an equalization signal; a first inverter having an input for receiving a first row address signal of the plurality of row address signals, and an output; a second inverter having an input coupled to the output of the first inverter, and an output; a first transistor having a first control electrode coupled to a first power supply terminal, a second current electrode coupled to the output of the first inverter, and a control electrode coupled to the output of the second inverter; a cross-coupled latch, coupled to the second inverter, for providing complementary outputs representative of the logic state of the first address signal; and transition detection means, coupled to the complementary outputs of the cross coupled latch, for initiating the equalization pulse in response to a transition from the first logic state to the second logic state of one of the complementary outputs.

Claim 11

A memory, comprising: a plurality of memory cells located at intersections of word lines and bit lines; a row decoder, coupled to the word lines, for enabling a selected word line as determined by a row address comprised of a plurality of row address signals at first or second logic states; equalization means, coupled to the bit lines, for equalizing the voltages on the bit lines in response to receiving an equalization signal; a first inverter having an input for receiving a first row address signal of the plurality of row address signals, and an output; a second inverter having an input coupled to the output of the first inverter, and an output; a first transistor having a first control electrode coupled to a first power supply terminal, a second current electrode coupled to the output of the first inverter, and a control electrode coupled to the output of the second inverter; a cross-coupled latch, coupled to the second inverter, for providing complementary outputs representative of the logic state of the first address signal; and transition detection means, coupled to the complementary outputs of the cross coupled latch, for initiating the equalization pulse in response to a transition from the first logic state to the second logic state of one of the complementary outputs.

Claim 12

The memory of claim 9 further comprising: a third inverter having an input coupled to the output of the second inverter, and an output; wherein the cross-coupled latch has a first input coupled to the output of the second inverter, and a second input coupled to the output of the third inverter.

Claim 13

The memory of claim 10 wherein the cross-coupled latch comprises: a first NAND gate having a first input coupled to the output of the second inverter, a second input, and an output for providing a first of the complementary outputs; and a second NAND gate having a first input coupled to the output of the third inverter, a second input coupled to the output of the first NAND gate, and an output connected to the second input of the first NAND gate for providing a second of the complementary outputs.

Claim 14

The memory of claim 11 wherein the first input of the first NAND gate has a first switch point and the third inverter has a second switch point, wherein the first switch point is greater than the second switch point.

Claim 15

The memory of claim 9 wherein the cross-coupled latch comprises: a first NAND gate having a first input coupled to the output of the second inverter, a second input, and an output for providing a first of the complementary outputs; and a second NAND gate having a first input coupled to the output of the first inverter, a second input coupled to the output of the first NAND gate, and an output connected to the second input of the first NAND gate for providing a second of the complementary outputs.

Claim 16

The memory of claim 13 wherein the first input of the second NAND gate has a first switch point and the second inverter has a second switch point, wherein the first switch point is greater than the second switch point.

Claim 17

The memory of claim 14 wherein the first inverter is a clocked inverter which is enabled by a chip select signal.

Claim 18

The memory of claim 15 wherein the clocked inverter is a NOR gate having a first input for receiving the first address signal, a second input for receiving the chip select signal, and an output coupled to the input of the second inverter.