Read-while-write ram cell

Claim 2

A nonsaturating differentially connected transistor memory cell comprising: first and second transistors, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; and a saturation prevention circuit including a third transistor having a collector, base, and first and second emitters, arranged such that said collector and said base of said third transistor are connected both together and to a fourth electrical voltage forming a fourth node, said first emitter of said third transistor connected to said first node and said second emitter of said third transistor connected to said second node, said saturation prevention circuit operative to turn on said third transistor to prevent saturation of said first and second transistors.

Claim 3

The circuit according to claim 1 wherein said second and third electrical voltages are the same.

Claim 4

The circuit according to claim 2 wherein said fourth electrical voltage is approximately one-half of a base-emitter voltage drop less then said second and third voltages.

Claim 5

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal; second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal; and a saturation prevention circuit including a third transistor having a collector, base, and first and second emitters, arranged such that said collector and said base of said third transistor are connected both together and to a fourth electrical voltage forming a fourth node, said first emitter of said third transistor connected to said first node and said second emitter of said third transistor connected to said second node, said saturation prevention circuit operative to turn on said third transistor to prevent saturation of said first and second transistors.

Claim 6

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal; second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal; and a saturation prevention circuit including a third transistor having a collector, base, and first and second emitters, arranged such that said collector and said base of said third transistor are connected both together and to a fourth electrical voltage forming a fourth node, said first emitter of said third transistor connected to said first node and said second emitter of said third transistor connected to said second node, said saturation prevention circuit operative to turn on said third transistor to prevent saturation of said first and second transistors.

Claim 7

The circuit according to claim 4 wherein said second and third electrical voltages are the same.

Claim 8

The circuit according to claim 5 wherein said fourth electrical voltage is approximately one-half of a base-emitter voltage drop less then said second and third voltages.

Claim 9

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal, said first means not substantially affecting current flow through said first and second transistors, and said first means further operative for supplying READ data outputs; and, second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal, said second means not substantially affecting total current flow through said first and second transistors, and said second means including means for supplying WRITE data inputs on lines different from those that supply READ data outputs.

Claim 10

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal, said first means not substantially affecting current flow through said first and second transistors, and said first means further operative for supplying READ data outputs; and, second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal, said second means not substantially affecting total current flow through said first and second transistors, and said second means including means for supplying WRITE data inputs on lines different from those that supply READ data outputs.

Claim 11

The circuit according to claim 7 wherein said second and third electrical voltages are the same.

Claim 12

The circuit according to claim 7, wherein said first means comprises: a third transistor having a collector, base, and emitter, arranged such that an access terminal connects to said collector of said third transistor, said base of said third transistor connects to said second node; a fourth transistor having a collector, base, and emitter, arranged such that said emitter of said fourth transistor connects to said emitter of said third transistor forming a fifth node, said collector of said fourth transistor connects to an access terminal, and said base of said fourth transistor connects to said first node; and a fifth transistor having a collector, base, and emitter, arranged such that said collector of said fifth transistor connects to said fifth node, said base of said fifth transistor connects to an access terminal, and said emitter of said fifth transistor connects to another access terminal; and wherein said second means comprises: a sixth transistor having a collector, base, and emitter, arranged such that an access terminal connects to said base of said sixth transistor, said collector of said sixth transistor connects to said second node; an seventh transistor having a collector, base, and emitter, arranged such that said emitter of said seventh transistor connects to said emitter of said sixth transistor forming a sixth node, said base of said seventh transistor connects to an access terminal, and said collector of said seventh transistor connects to said first node; and an eighth transistor having a collector, base, and emitter, arranged such that said collector of said eighth transistor connects to said sixth node, said base of said eighth transistor connects to an access terminal, and said emitter of said eighth transistor connects to another access terminal.

Claim 13

The circuit according to claim 9 wherein said second and third electrical voltages are the same.

Claim 14

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal, said first means not substantially affecting current flow through said first and second transistors, and said first means further operative for supplying READ data outputs; and, second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal, said second means not substantially affecting total current flow through said first and second transistors, and said second means including means for supplying WRITE data inputs on lines different from those that supply READ data outputs; and a saturation prevention circuit including a third transistor having a collector, base, and first and second emitters, arranged such that said collector and said base of said third transistor are connected both together and to a fourth electrical voltage forming a fourth node, said first emitter of said third transistor connected to said first node and said second emitter of said third transistor connected to said second node, said saturation prevention circuit operative to turn on said third transistor to prevent saturation of said first and second transistors.

Claim 15

A READ-WHILE-WRITE bipolar memory cell for storing a single data bit, comprising: first and second transistors for storing said data bit, each having a collector, base and emitter, arranged such that said collector of said first transistor is connected to said base of said second transistor forming a first node, said collector of said second transistor is connected to said base of said first transistor forming a second node, and said emitters of said first and second transistors are connected together forming a third node; a constant current source coupled between said third node and a first electrical voltage establishing a predetermined substantially constant current through said third node wherein the sum of the currents through said first and second transistor emitters are restricted by said constant current source; a first load providing an impedance coupled between said first node and a second electrical voltage; a second load providing an impedance coupled between said second node and a third electrical voltage; first means for sensing said data bit stored in said first and second transistors in response to a READ signal, said first means not substantially affecting current flow through said first and second transistors, and said first means further operative for supplying READ data outputs; and, second means for setting said data bit to be stored in said first and second transistors in response to a WRITE signal, said second means not substantially affecting total current flow through said first and second transistors, and said second means including means for supplying WRITE data inputs on lines different from those that supply READ data outputs; and a saturation prevention circuit including a third transistor having a collector, base, and first and second emitters, arranged such that said collector and said base of said third transistor are connected both together and to a fourth electrical voltage forming a fourth node, said first emitter of said third transistor connected to said first node and said second emitter of said third transistor connected to said second node, said saturation prevention circuit operative to turn on said third transistor to prevent saturation of said first and second transistors.

Claim 16

The circuit according to claim 11 wherein said first means comprises: a fourth transistor having a collector, base, and emitter, arranged such that an access terminal connects to said collector of said fourth transistor, said base of said fourth transistor connects to said second node; a fifth transistor having a collector, base, and emitter, arranged such that said emitter of said fifth transistor connects to said emitter of said fourth transistor forming a fifth node, said collector of said fifth transistor connects to an access terminal, and said base of said fourth transistor connects to said first node; and a sixth transistor having a collector, base, and emitter, arranged such that said collector of said sixth transistor connects to said fifth node, said base of said sixth transistor connects to an access terminal, and said emitter of said sixth transistor connects to another access terminal; and wherein said second means comprises: a seventh transistor having a collector, base, and emitter, arranged such that an access terminal connects to said base of said seventh transistor, said collector of said seventh transistor connects to said second node; and, an eighth transistor having a collector, base, and emitter, arranged such that said emitter of said eighth transistor connects to said emitter of said seventh transistor forming a sixth node, said base of said eighth transistor connects to an access terminal, and said collector of said eighth transistor connects to said first node; a ninth transistor having a collector, base, and emitter, arranged such that said collector of said ninth transistor connects to said sixth node, said base of said ninth transistor connects to an access terminal, and said emitter of said ninth transistor connects to another access terminal.

Claim 17

The circuit according to claim 12 wherein said constant current source comprises: a tenth transistor having a collector, base, and emitter, and a first resistor arranged such that said first resistor connects between said emitter of said tenth transistor and said first electrical voltage, said collector of said tenth transistor connects to said third node, and said base of said tenth transistor connects to a fifth electrical voltage, said fifth electrical voltage sets the current magnitude through said constant current source to a predetermined value.

Claim 18

The circuit according to claim 12 wherein said second and third electrical voltages are the same.

Claim 19

The circuit according to claim 14 wherein said fourth electrical voltage is approximately one-half of a base-emitter voltage drop less then said second and third voltages.

Claim 20

The circuit according to claim 15 wherein said constant current source comprises: a tenth transistor having a collector, base, and emitter, and a first resistor arranged such that said first resistor connects between said emitter of said tenth transistor and said first electrical voltage, said collector of said tenth transistor connects to said third node, and said base of said tenth transistor connects to a fifth electrical voltage, said fifth electrical voltage sets the current magnitude through said constant current source to a predetermined value.