Dynamic random access memory having folded bit line-shared sense amplifiers

Claim 1

A DRAM having folded bit line-shared sense amplifiers comprising a first array of memory cells; a second array of memory cells; an array of sense amplifiers provided between and shared by said memory cell arrays; a plurality of bit line pairs, each pair having connected therebetween a different memory cell of the first array, a different sense amplifier, and a different memory cell of the second array and wherein the bit line pairs are divided into at least a first group and a second group; separate input/output means connected to each bit line pair at one end to selectively transfer data to each bit line pair; separate first switch means provided in series with each bit line pair of the first group between the memory cell of first array and the sense amplifier; separate second switch means provided in series with each bit line pair of the second group between the memory cell of first array and the sense amplifier; and separate third switch means provided in series with each bit line pair between and separating the memory cell of the second array and the sense amplifier from each other; and wherein the first switch means, the second switch means and the third switch means are responsive to separate control signals.