US4656495A
Expired / Lapsed
US
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Bipolar ram cell and process
Assignee: Motorola Solutions Inc
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Filing: 1985-07-01
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Granted: 1987-04-07
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Expires: 2005-07-01
Abstract
Abstract An integrated bipolar RAM cell and process for its manufacture is disclosed. The RAM cell includes first and second cross-coupled bipolar transistors with first and second load elements coupled to the collectors of the first and second transistors, respectively. The load elements can be, for example, diode clamped resistors or lateral PNP transistors. The load elements include regions which are capable of injecting minority carriers into the collectors of the first and second transistors. To avoid charge storage problems and associated reduced switching speed while maintaining high voltage noise immunity, the charge injecting regions are fabricated having an integrated impurity doping less than or equal to about 1×10 13 cm -2 .
Inventors
- 👤 Mark S. Birrittella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:22
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
132 words
An integrated bipolar RAM cell comprising: first and second cross-coupled multiple emitter NPN transistors, the base of said first transistor coupled to the collector of said second transistor and the base of said second transistor coupled to the collector of said first transistor, a first emitter of said first transistor coupled to a first bit line and a first emitter of said second transistor coupled to a second bit line, a second emitter of each of said first and second transistors coupled to current generator means; first and second PNP transistors coupled between the collector of said first and second transistors, respectively, and a word line, said first and second PNP transistors having emitter regions characterized by an integrated impurity doping less than or equal to about 1×10 13 cm -2 .
Claim 2
Dependent Claim
132 words
An integrated bipolar RAM cell comprising: first and second cross-coupled multiple emitter NPN transistors, the base of said first transistor coupled to the collector of said second transistor and the base of said second transistor coupled to the collector of said first transistor, a first emitter of said first transistor coupled to a first bit line and a first emitter of said second transistor coupled to a second bit line, a second emitter of each of said first and second transistors coupled to current generator means; first and second PNP transistors coupled between the collector of said first and second transistors, respectively, and a word line, said first and second PNP transistors having emitter regions characterized by an integrated impurity doping less than or equal to about 1×10 13 cm -2 .
Claim 3
Dependent Claim
79 words
An integrated bipolar RAM cell which comprises: first and second cross-coupled bipolar transistors; and first and second PNP transistors coupled to the collectors of said first and second transistors, respectively, said PNP transistors including emitter regions capable of injection minority carriers into the collectors of said first and second transistors, said emitter regions forming PN junctions with said collectors, said emitter regions characterized by an integrated impurity doping less than or equal to about 1×10 13 cm -2 .
Claim 4
Dependent Claim
79 words
An integrated bipolar RAM cell which comprises: first and second cross-coupled bipolar transistors; and first and second PNP transistors coupled to the collectors of said first and second transistors, respectively, said PNP transistors including emitter regions capable of injection minority carriers into the collectors of said first and second transistors, said emitter regions forming PN junctions with said collectors, said emitter regions characterized by an integrated impurity doping less than or equal to about 1×10 13 cm -2 .
Claim 5
Dependent Claim
35 words
The RAM cell of claim 2 wherein one of said first and second bipolar transistors and one of said first and second PNP transistors are positioned in an isolated surface region of a semiconductor substrate.
References Cited (Backward Citations)
US4045248A
Cited
EP0029717A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-06 | 1990-10-06 | 1991-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-06 | 1994-10-06 | 1995-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-06 | 1998-10-06 | 1999-04-07 | $7700.00 | Window Closed / Lapsed |