US4580244A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar memory cell
Assignee: NXP USA Inc
•
Filing: 1984-06-21
•
Granted: 1986-04-01
•
Expires: 2004-06-21
Abstract
Abstract A monolithically integrated memory cell having an improved clamped diode load is provided for improving write pulse width and write recovery times. A pair of latchable cross-coupled multi-emitter NPN transistors have a first emitter connected to a stand-by current drain line, and a second emitter coupled to a first bit line and a second bit line, respectively. The base of each transistor is cross-coupled to the collector of the other transistor. The base of each transistor is further coupled to the select line by a PNP transistor. The base of each PNP transistor is coupled to the collector of the respective cross-coupled transistor and is further coupled to the select line by a diode connected NPN transistor. The architecture of the diode connected NPN transistor in the chip prevents substantial stored charge buildup in the epi layer resulting in a lower voltage margin than previously known PN diode or PNP transistor loaded cells, and a higher voltage margin than the previously known Schottky diode loaded cell without the disturb sensitivity.
Inventors
- 👤 Mark S. Birrittella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
131 words
An improved bipolar memory cell having first and second multi-emitter cross-coupled transistors and first means for implementing a non-linear resistance coupled between a select line and both a base of said first multi-emitter transistor and a collector of said second multi-emitter transistor, and second means for implementing a non-linear resistance coupled between said select line and both a base of said second multi-emitter transistor and a collector of said first multi-emitter transistor, wherein the improvement comprises a first NPN transistor having a collector and a base coupled to said select line and an emitter coupled to said collector of said first multi-emitter transistor; and a second NPN transistor having a collector and a base coupled to said select line and an emitter coupled to said collector of said second multi-emitter transistor.
Claim 2
Dependent Claim
131 words
An improved bipolar memory cell having first and second multi-emitter cross-coupled transistors and first means for implementing a non-linear resistance coupled between a select line and both a base of said first multi-emitter transistor and a collector of said second multi-emitter transistor, and second means for implementing a non-linear resistance coupled between said select line and both a base of said second multi-emitter transistor and a collector of said first multi-emitter transistor, wherein the improvement comprises a first NPN transistor having a collector and a base coupled to said select line and an emitter coupled to said collector of said first multi-emitter transistor; and a second NPN transistor having a collector and a base coupled to said select line and an emitter coupled to said collector of said second multi-emitter transistor.
Claim 3
Dependent Claim
73 words
The improved bipolar memory cell according to claim 1 wherein said first means and said second means comprise a first and a second PNP transistor, said first PNP transistor having a base coupled to said collector of said first multi-emitter transistor and said emitter of said first NPN transistor, said second PNP transistor having a base coupled to said collector of said second multi-emitter transistor and said emitter of said second NPN transistor.
Claim 4
Dependent Claim
19 words
The improved bipolar memory cell according to claim 1 wherein said first means and said second means are resistors.
Claim 5
Dependent Claim
202 words
The improved bipolar memory cell according to claim 2 wherein each of both said first NPN transistor and said first PNP transistor, and both said second NPN transistor and said second PNP transistor comprise a monolithically integrated structure comprising: a first region having a first conductivity type; a second region having a second conductivity type formed at a surface of and within said first region; a third region having said first conductivity type formed at a surface of and within a first portion of said second region; a fourth region having said first conductivity type formed at a surface of and within a second portion of said second region; a fifth region having said second conductivity type formed at a surface of and within said third region; a sixth region having said second conductivity type formed at a surface of and within a first portion of said fourth region; a seventh region having said second conductivity type formed at a surface of and within a second portion of said fourth region; and an eighth region formed at a surface of at least a portion of said third region and a portion of said fifth region, said eight region comprising a conductive material.
Claim 6
Dependent Claim
238 words
The improved bipolar memory cell according to claim 3 wherein each of both said first NPN transistor and one of said resistors, and both said second NPN transistor and the other of said resistors comprise a monolithically integrated structure comprising: a first region having a first conductivity type; a second region having a second conductivity type formed at a surface of and within said first region; a third region having said first conductivity type formed at a surface of and within a first portion of said second region; a fourth region having said first conductivity type formed at a surface of and within a second portion of said second region; a fifth region having said second conductivity type formed at a surface of and within said third region; a sixth region having said second conductivity type formed at a surface of and within a first portion of said fourth region; a seventh region having said second conductivity type formed at a surface of and within a second portion of said fourth region; an eighth region formed at a surface of at least a portion of said third region and a portion of said fifth region, said eight region comprising a conductive material; and a ninth region having said first conductivity type formed at a surface of and within a third portion of said second region, said ninth region contiguously positioned between said third region and said fourth region.
Claim 7
Dependent Claim
55 words
The improved bipolar memory cell according to claim 4 further comprising a ninth region having a second conductivity type, said ninth region being more heavily doped than said second region, said ninth region formed at a surface of and within said first region, and said second region formed at a surface of said ninth region.
Claim 8
Dependent Claim
55 words
The improved bipolar memory cell according to claim 5 further comprising a tenth region having a second conductivity type, said tenth region being more heavily doped than said second region, said tenth region formed at a surface of and within said first region, and said second region formed at a surface of said tenth region.
Claim 9
Dependent Claim
55 words
The improved bipolar memory cell according to claim 6 further comprising a tenth region having a second conductivity type, said tenth region being more heavily doped than said second region, said tenth region formed at a portion of a surface of said ninth region and extending through said second region to a third portion thereof.
Claim 10
Dependent Claim
55 words
The improved bipolar memory cell according to claim 7 further comprising an eleventh region having a second conductivity type, said eleventh region being more heavily doped than said second region, said eleventh region formed at a portion of a surface of said tenth region and extending through said second region to a fourth portion thereof.
Claim 11
Dependent Claim
236 words
A memory cell having a first bit line, a second bit line, a select line, and a stand-by current line, comprising: a first transistor having a base, a collector, a first emitter, and a second emitter, said first emitter coupled to said first bit line, said second emitter coupled to said stand-by current line; a second transistor having a base, a collector, a first emitter, and a second emitter, said first emitter coupled to said second bit line, said first emitter coupled to said second bit line, said second emitter coupled to said stand-by current line, said base coupled to said collector of said first transistor and said collector coupled to said base of said first transistor; first means for implementing a non-linear resistance coupled between said select line and both a base of said first transistor and a collector of said second transistor; second means for implementing a non-linear resistance coupled between said select line and both a base of said second transistor and a collector of said first transistor; a third transistor having a base and a collector coupled to said select line, and an emitter coupled to said collector of said first transistor and said base of said second transistor; and a fourth transistor having a base and a collector coupled to said select line, and said emitter coupled to said base of said first transistor and said collector of said second transistor.
Claim 12
Dependent Claim
236 words
A memory cell having a first bit line, a second bit line, a select line, and a stand-by current line, comprising: a first transistor having a base, a collector, a first emitter, and a second emitter, said first emitter coupled to said first bit line, said second emitter coupled to said stand-by current line; a second transistor having a base, a collector, a first emitter, and a second emitter, said first emitter coupled to said second bit line, said first emitter coupled to said second bit line, said second emitter coupled to said stand-by current line, said base coupled to said collector of said first transistor and said collector coupled to said base of said first transistor; first means for implementing a non-linear resistance coupled between said select line and both a base of said first transistor and a collector of said second transistor; second means for implementing a non-linear resistance coupled between said select line and both a base of said second transistor and a collector of said first transistor; a third transistor having a base and a collector coupled to said select line, and an emitter coupled to said collector of said first transistor and said base of said second transistor; and a fourth transistor having a base and a collector coupled to said select line, and said emitter coupled to said base of said first transistor and said collector of said second transistor.
Claim 13
Dependent Claim
172 words
A monolithically integrated memory cell including two half cells, wherein each of said half cells comprise: a first region having a first conductivity type; a second region having a second conductivity type formed at a surface of and within said first region; a third region having said first conductivity type formed at a surface of and within a first portion of said second region; a fourth region having said first conductivity type formed at a surface of and within a second portion of said second region; a fifth region having said second conductivity type formed at a surface of and within said third region; a sixth region having said second conductivity type formed at a surface of and within a first portion of said fourth region; a seventh region having said second conductivity type formed at a surface of and within a second portion of said fourth region; and an eighth region overlying at least a portion of said third region and said fifth region, said eighth region comprising a conductive material.
Claim 14
Dependent Claim
172 words
A monolithically integrated memory cell including two half cells, wherein each of said half cells comprise: a first region having a first conductivity type; a second region having a second conductivity type formed at a surface of and within said first region; a third region having said first conductivity type formed at a surface of and within a first portion of said second region; a fourth region having said first conductivity type formed at a surface of and within a second portion of said second region; a fifth region having said second conductivity type formed at a surface of and within said third region; a sixth region having said second conductivity type formed at a surface of and within a first portion of said fourth region; a seventh region having said second conductivity type formed at a surface of and within a second portion of said fourth region; and an eighth region overlying at least a portion of said third region and said fifth region, said eighth region comprising a conductive material.
Claim 15
Dependent Claim
46 words
The monolithically integrated memory cell according to claim 11, further comprising a ninth region having said first conductivity type formed at a surface of and within a third portion of said second region, said ninth region positioned contiguously between said third region and said fourth region.
Claim 16
Dependent Claim
100 words
The monolithically integrated memory cell according to claim 11, further comprising: a ninth region having a second conductivity type, said ninth region being more heavily doped than said second region, said ninth region formed at a surface of and within said first region, and said second region formed at a surface of said ninth region; and a tenth region having a second conductivity type, said tenth region being more heavily doped than said second region, said tenth region formed at a portion of a surface of said ninth region and extending through said second region to a third portion thereof.
Claim 17
Dependent Claim
100 words
The monolithically integrated memory cell according to claim 12, further comprising: a tenth region having a second conductivity type, said tenth region being more heavily doped than said second region, said tenth region formed at a surface of and within said first region, and said second region formed at a surface of said tenth region; and an eleventh region having a second conductivity type, said eleventh region being more heavily doped than said second region, said eleventh region formed at a portion of a surface of said tenth region and extending through said second region to a third portion thereof.
References Cited (Backward Citations)
US4311925A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |