US4701883A
Expired / Lapsed
US
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ECL/CMOS memory cell with separate read and write bit lines
Assignee: Motorola Solutions Inc
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Filing: 1986-06-19
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Granted: 1987-10-20
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Expires: 2006-06-19
Abstract
Abstract A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.
Inventors
- 👤 Robert S. Wrathall
- 👤 Kevin L. McLaughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
248 words
A memory cell comprising: first, second, third and fourth transistors each having a control terminal and first and second load terminals, said first load terminals of said first and second transistors coupled together for connection to a first word line terminals, said first load terminals of said third and fourth transistors coupled together for connection to a second word line terminal; a fifth transistor having a control terminal and first and second load terminals, said first load terminal of said fifth transistor coupled to a source of supply voltage and said second load terminal of said fifth transistor for coupling to a first bit line; a first diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said first, third and fifth transistors and to said second load terminals of said second and fourth transistors, said cathode terminal of said first diode for coupling to a second bit line; a sixth transistor having a control terminal and first and second load terminals, said first load terminal of said sixth transistor coupled to said source of supply voltage and said second load terminal of said sixth transistor coupled to a complemented first bit line; and a second diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said second, fourth and sixth transistors and to said second load terminals of said first and third transistors, said cathode terminal of said second diode coupled to a complemented second bit line.
Claim 2
Dependent Claim
248 words
A memory cell comprising: first, second, third and fourth transistors each having a control terminal and first and second load terminals, said first load terminals of said first and second transistors coupled together for connection to a first word line terminals, said first load terminals of said third and fourth transistors coupled together for connection to a second word line terminal; a fifth transistor having a control terminal and first and second load terminals, said first load terminal of said fifth transistor coupled to a source of supply voltage and said second load terminal of said fifth transistor for coupling to a first bit line; a first diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said first, third and fifth transistors and to said second load terminals of said second and fourth transistors, said cathode terminal of said first diode for coupling to a second bit line; a sixth transistor having a control terminal and first and second load terminals, said first load terminal of said sixth transistor coupled to said source of supply voltage and said second load terminal of said sixth transistor coupled to a complemented first bit line; and a second diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said second, fourth and sixth transistors and to said second load terminals of said first and third transistors, said cathode terminal of said second diode coupled to a complemented second bit line.
Claim 3
Dependent Claim
17 words
The memory cell of claim 1 wherein said first, second, third and fourth transistors are CMOS transistors.
Claim 4
Dependent Claim
15 words
The memory cell of claim 1 wherein said fifth and sixth transistors are bipolar transistors.
Claim 5
Dependent Claim
15 words
The memory cell of claim 2 wherein said fifth and sixth transistors are bipolar transistors.
Claim 6
Dependent Claim
15 words
The memory cell of claim 4 wherein said fifth and sixth transistors are NPN transistors.
Claim 7
Dependent Claim
27 words
The memory cell of claim 2 wherein said first, second, third, fourth and fifth transistors and said first and second diodes are contained in an integrated circuit.
Claim 8
Dependent Claim
42 words
The memory cell of claim 2 wherein said control terminals of said first, second, third and fourth transistors are gate terminals and said first and second load terminals of said first, second third and fourth transistors are source and drain terminals, respectively.
Claim 9
Dependent Claim
16 words
The memory cell of claim 1 wherein said first and second diodes are emitter base diodes.
Claim 10
Dependent Claim
15 words
The memory cell of claim 1 wherein said first and second diodes are Schottky diodes.
Claim 11
Dependent Claim
26 words
The memory cell of claim 6 wherein said fifth and sixth transistors are respectively merged with the second load terminals of said second and first transistors.
Claim 12
Dependent Claim
26 words
The memory cell of claim 6 wherein said first and second diodes, are respectively merged with said second load terminals of said fourth and third transistors.
Claim 13
Dependent Claim
314 words
In a memory cell comprising: first, second third and fourth transistors, each having a control terminal and first and second load terminals, said first load terminals of said first and second transistors coupled together for connection to a first word line terminal, said first load terminals of said third and fourth transistors coupled together for connection to a second word line terminal, said control terminals of said first and third transistors coupled together and coupled to said second load terminals of said second and fourth transistors for coupling to a first bit line, and said control terminals of said second and fourth transistors coupled together and to said second load terminals of said first and third transistors for coupling to a complemented first bit line, the improvement comprising: a fifth transistor having a control terminal and first and second load terminals, said first load terminal of said fifth transistor coupled to a source of supply voltage and said load terminal of said fifth transistor for coupling to said first bit line; a first diode having anode and cathode terminals, said anode terminal coupled to said control terminals of said first, third and fifth transistors and to said second load terminals of said second and fourth transistors, said cathode terminal of said first diode for coupling to a second bit line; a sixth transistor having a control terminal and first and second load terminals, said first load terminal of said sixth transistor coupled to said source of supply voltage and said second load terminal of said sixth transistor coupled to said complemented first bit line; and a second diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said second, fourth and sixth transistors and to said second load terminals of said first and third transistors, said cathode terminal of said second diode coupled to a complemented second bit line.
Claim 14
Dependent Claim
314 words
In a memory cell comprising: first, second third and fourth transistors, each having a control terminal and first and second load terminals, said first load terminals of said first and second transistors coupled together for connection to a first word line terminal, said first load terminals of said third and fourth transistors coupled together for connection to a second word line terminal, said control terminals of said first and third transistors coupled together and coupled to said second load terminals of said second and fourth transistors for coupling to a first bit line, and said control terminals of said second and fourth transistors coupled together and to said second load terminals of said first and third transistors for coupling to a complemented first bit line, the improvement comprising: a fifth transistor having a control terminal and first and second load terminals, said first load terminal of said fifth transistor coupled to a source of supply voltage and said load terminal of said fifth transistor for coupling to said first bit line; a first diode having anode and cathode terminals, said anode terminal coupled to said control terminals of said first, third and fifth transistors and to said second load terminals of said second and fourth transistors, said cathode terminal of said first diode for coupling to a second bit line; a sixth transistor having a control terminal and first and second load terminals, said first load terminal of said sixth transistor coupled to said source of supply voltage and said second load terminal of said sixth transistor coupled to said complemented first bit line; and a second diode having anode and cathode terminals, said anode terminal coupled to the control terminals of said second, fourth and sixth transistors and to said second load terminals of said first and third transistors, said cathode terminal of said second diode coupled to a complemented second bit line.
Claim 15
Dependent Claim
17 words
The memory cell of claim 12 wherein said first, second, third and fourth transistors are CMOS transistors.
Claim 16
Dependent Claim
15 words
The memory cell of claim 13 wherein said fifth and sixth transistors are bipolar transistors.
Claim 17
Dependent Claim
28 words
The memory cell of claim 14 wherein said first, second, third, fourth, fifth and sixth transistors and said first and second diodes are contained in an integrated circuit.
Claim 18
Dependent Claim
25 words
The circuit of claim 15 wherein said fifth and sixth transistors are respectively merged into the second load terminals of said second and first transistors.
Claim 19
Dependent Claim
25 words
The circuit of claim 16 wherein said first and second diodes are respectively merged into the second load terminals of said fourth and third transistors.
References Cited (Backward Citations)
US4630238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |