Non-volatile memory, semiconductor memory device having the non-volatile memory

Claim 2

A non-volatile memory device comprising: a semiconductor layer; a first insulating film formed on said semiconductor layer; floating gates formed on said first insulating film; a second insulating film formed on said floating gates; control gates respectively formed on said second insulating film and located above respective said floating gates; pairs of first and second impurity diffused layers formed in said semiconductor layer and located on respective, opposite sides of corresponding said control gates; word lines electrically connected to respective said control gates; bit lines electrically connected to respective, said first impurity diffused layers and extending perpendicularly with respect to said word lines; wiring electrodes electrically connected to respective, said second impurity diffused layers, said wiring electrodes extending in a common direction in which said bit lines extend; and said pairs of first and second impurity diffused layers being formed in corresponding areas of said semiconductor layer, said areas extending obliquely with respect to said bit lines.

Claim 3

A non-volatile memory device as claimed in claim 1, wherein said areas extend in a zigzag pattern of successive and oppositely oriented areas, each area forming an oblique angle with respect to said bit lines.

Claim 4

A non-volatile memory device as claimed in claim 1, wherein said wiring electrodes and said bit lines are formed on respective, different insulator films.

Claim 5

A non-volatile memory device as claimed in claim 3, wherein each of said wiring electrodes has a fin-shaped structure comprising at least one vertical portion and at least one fin, said at least one vertical portion being connected to one of the second impurity diffused layers and said at least one fin extending substantially horizontally from a corresponding said vertical portion.

Claim 6

A non-volatile memory device as claimed in claim 2, wherein said bit liens are in contact with respective, said first impurity diffused layers, each bit line contacting a corner portion of each of said respectively corresponding areas of said zigzag pattern.

Claim 7

A semiconductor memory device comprising: a semiconductor layer; a first insulating film formed on said semiconductor layer; floating gates formed on said first insulating film; a second insulating film formed on said floating gates; control gates respectively formed on said second insulating film and located above respective said floating gates; pairs of first and second impurity diffused layers formed in said semiconductor layer and located on respective, opposite sides of corresponding said control gates; first wold lines electrically connected to respective said control gates; first bit lines electrically connected to respective, said first impurity diffused layers and extending perpendicularly with respect to said word lines; wiring electrodes electrically connected to respective, said second impurity diffused layers; said control gates, said floating gates, said pairs of first and second impurity diffused layers, said first word lines, and said first bit lines forming non-volatile memory elements, said wiring electrodes extending in a common direction in which said first bit lines extend; second word lines formed on said first insulating layer; pairs of third and fourth impurity diffused layers formed in said semiconductor layer and located on respective, opposite sides of corresponding said second word lines; second bit lines electrically connected to respective, said third impurity diffused layers; capacitor electrically connected to respective, said fourth impurity diffused layers, said capacitors including corresponding storage electrodes; said second word lines, said pairs of third and fourth impurity diffused layers, said second bit liens, and said capacitors forming volatile memory elements; and said storage electrodes and said wiring electrodes being formed from a common, first conductive layer.

Claim 8

A semiconductor memory device comprising: a semiconductor layer; a first insulating film formed on said semiconductor layer; floating gates formed on said first insulating film; a second insulating film formed on said floating gates; control gates respectively formed on said second insulating film and located above respective said floating gates; pairs of first and second impurity diffused layers formed in said semiconductor layer and located on respective, opposite sides of corresponding said control gates; first wold lines electrically connected to respective said control gates; first bit lines electrically connected to respective, said first impurity diffused layers and extending perpendicularly with respect to said word lines; wiring electrodes electrically connected to respective, said second impurity diffused layers; said control gates, said floating gates, said pairs of first and second impurity diffused layers, said first word lines, and said first bit lines forming non-volatile memory elements, said wiring electrodes extending in a common direction in which said first bit lines extend; second word lines formed on said first insulating layer; pairs of third and fourth impurity diffused layers formed in said semiconductor layer and located on respective, opposite sides of corresponding said second word lines; second bit lines electrically connected to respective, said third impurity diffused layers; capacitor electrically connected to respective, said fourth impurity diffused layers, said capacitors including corresponding storage electrodes; said second word lines, said pairs of third and fourth impurity diffused layers, said second bit liens, and said capacitors forming volatile memory elements; and said storage electrodes and said wiring electrodes being formed from a common, first conductive layer.

Claim 9

A semiconductor memory device as claimed in claim 6, wherein said second word lines and said control gates are formed from a common, second conductive layer.

Claim 10

A semiconductor memory device as claimed in claim 6, wherein said first bit lines and said second bit lines are formed from a common, third conductive layer.

Claim 11

A semiconductor memory device as claimed in claim 6, wherein said pairs of first and second impurity diffused layers are formed in corresponding areas of said semiconductor layer, said areas extending obliquely with respect to said first bit lines.

Claim 12

A semiconductor memory device as claimed in claim 6, wherein each of said wiring electrodes has a first fin-shaped structure, and each of said storage electrodes has a second fin-shaped structure.

Claim 13

A semiconductor memory device as claimed in claim 10, wherein each of said first fin-shaped structure and said second fins-shaped structure has a common number of fins.