Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion

Claim 2

A parallel conduction path circuit connected to a fast-switching driving stage to slow down a signal switching transition period defined as the period of a logic state switching operation when an input signal received by the driving stage is inverted so as to transmit from a first steady-state logic level to a second steady-state logic level, the driving stage including one of a pull-up and a pull-down circuits and being connected to detect a transition of the input signal received at an input node thereof and in response to which said logic state switching operation is initiated, the parallel conduction path circuit comprising: a conducting circuit portion connected to the driving stage and serving as a variable current conduction path thereto, the conducting circuit portion providing maximum current intensity during an initial period of said switching transition period and selectively providing a non-zero current intensity, which is less than the maximum current intensity, a predetermined period of time into the switching transition period; and a delay circuit portion, coupled to the input node to receive the input signal simultaneously with the driving stage, said delay circuit portion controlling, in response to the input signal, the conducting circuit portion so as to provide the non-zero current intensity to said driving stage at the predetermined period of time into the switching transition period, whereby the non-zero current intensity operates to provide a longer switching transition period than if the current intensity had not been reduced from the maximum intensity.

Claim 3

A parallel conduction path circuit according to claim 1, wherein said driving stage is a pull-up transistor stage of a data buffer circuit, and wherein said conducting circuit portion provides a variable current conduction path to a gate of a pull-up driving transistor associated with said pull-up transistor stage.

Claim 4

A parallel conduction path circuit according to claim 1, wherein said driving stage is a pull-down transistor stage of a data buffer circuit, and wherein said conducting circuit portion provides a variable current conduction path to a gate of a pull-down driving transistor associated with said pull-down transistor stage.

Claim 5

A parallel conduction path circuit according to claim 1, wherein said delay circuit portion includes serially-connected first, second and third inverters coupled to receive said input signal.

Claim 6

A parallel conduction path circuit according to claim 2, wherein said conducting circuit portion comprises: a first NMOS transistor having a gate electrode coupled to receive an output signal from said delay circuit portion, a drain electrode connected to a source electrode of said driving stage and a source electrode connected to the ground potential; and a second NMOS transistor having a gate electrode applied with a constant voltage source, and a drain electrode and a source electrode respectively connected to the drain electrode and source electrode of said first NMOS transistor.

Claim 7

A parallel conduction path circuit according to claim 3, wherein said conducting circuit portion comprises: a first PMOS transistor having a gate electrode coupled to receive an output signal from said delay circuit portion, a drain electrode connected to a source electrode of said driving stage and a source electrode connected to a constant voltage source; and a second PMOS transistor having a gate electrode applied with a ground potential, and a drain electrode and a source electrode respectively connected to the drain electrode and source electrode of said first NMOS transistor.

Claim 8

A parallel conduction path circuit according to claim 5, wherein said delay circuit portion includes serially-connected first, second and third inverters coupled to receive said input signal.

Claim 9

A parallel conduction path circuit according to claim 6, wherein said delay circuit portion includes serially-connected first, second and third inverters coupled to receive said input signal.

Claim 10

A parallel conduction path circuit according to claim 7, wherein said conducting circuit portion further comprises a PMOS transistor having a gate electrode receiving the output signal of said second inverter, and a drain electrode and a source electrode respectively connected to the source electrode and drain electrode of said first NMOS transistor.

Claim 11

A parallel conduction path circuit according to claim 8, wherein said conducting circuit portion further comprises a NMOS transistor having a gate electrode receiving the output signal of said second inverter, and a drain electrode and a source electrode respectively connected to the source electrode and drain electrode of said first PMOS transistor.

Claim 12

A data buffer circuit including first and second parallel conduction path circuits respectively connected to a pull-up transistor stage and a pull-down transistor stage, to slow down a signal switching transition period defined as the period of a logic state switching operation when a respective input signal received by one of the pull-up and pull-down transistor stages is respectively inverted so as to transit from a first steady-state logic level to a second steady-state logic level, each of the pull-up and pull-down transistor stages being connected to detect a transition of the respective input signal received at an input node thereof and in response to which said logic state switching operation is initiated, each of said first and second parallel conduction path circuits comprising: a conducting circuit portion connected to the corresponding transistor stage and serving as a variable current conduction path thereto, the conducting circuit portion providing maximum current intensity during an initial period of said switching transition period and selectively providing a non-zero current intensity, which is less than the maximum current intensity, a predetermined period of time into the switching transition period; and a delay circuit portion, coupled to the input node to receive the input signal simultaneously with the driving stage, said delay circuit portion controlling, in response to the input signal, the conducting circuit portion so as to provide the non-zero current intensity to said driving stage at the predetermined period of time into the switching transition period, whereby the non-zero current intensity operates to provide a longer switching transition period than if the current intensity had not been reduced from the maximum intensity.

Claim 13

A data buffer circuit including first and second parallel conduction path circuits respectively connected to a pull-up transistor stage and a pull-down transistor stage, to slow down a signal switching transition period defined as the period of a logic state switching operation when a respective input signal received by one of the pull-up and pull-down transistor stages is respectively inverted so as to transit from a first steady-state logic level to a second steady-state logic level, each of the pull-up and pull-down transistor stages being connected to detect a transition of the respective input signal received at an input node thereof and in response to which said logic state switching operation is initiated, each of said first and second parallel conduction path circuits comprising: a conducting circuit portion connected to the corresponding transistor stage and serving as a variable current conduction path thereto, the conducting circuit portion providing maximum current intensity during an initial period of said switching transition period and selectively providing a non-zero current intensity, which is less than the maximum current intensity, a predetermined period of time into the switching transition period; and a delay circuit portion, coupled to the input node to receive the input signal simultaneously with the driving stage, said delay circuit portion controlling, in response to the input signal, the conducting circuit portion so as to provide the non-zero current intensity to said driving stage at the predetermined period of time into the switching transition period, whereby the non-zero current intensity operates to provide a longer switching transition period than if the current intensity had not been reduced from the maximum intensity.

Claim 14

A parallel conduction path circuit according to claim 11, wherein said conducting circuit portion associated with the pull-up transistor stage of said data buffer circuit comprises: a first NMOS transistor having a gate electrode coupled to receive an output signal from the delay circuit portion associated with the pull-up transistor stage, a drain electrode connected to a source electrode of said pull-up transistor stage and a source electrode connected to the ground potential; and a second NMOS transistor having a gate electrode applied with a constant voltage source, and a drain electrode and a source electrode respectively connected to the drain electrode and source electrode of said first NMOS transistor; and wherein said conducting circuit portion associated with the pull-down transistor stage of said data buffer circuit comprises: a first PMOS transistor having a gate electrode coupled to receive an output signal from the delay circuit portion, a drain electrode connected to a source electrode of said driving stage and a source electrode connected to a constant voltage source; and a second PMOS transistor having a gate electrode applied with a ground potential, and a drain electrode and a source electrode respectively connected to the drain electrode and source electrode of said first NMOS transistor.

Claim 15

A parallel conduction path circuit according to claim 12, wherein each corresponding delay circuit portion includes serially-connected first, second and third inverters coupled to receive the corresponding input signal.

Claim 16

A parallel conduction path circuit according to claim 13, wherein the conducting circuit portion associated with said first pull-up transistor stage further comprises a PMOS transistor having a gate electrode receiving the output signal of said second inverter, and a drain electrode and a source electrode respectively connected to the source electrode and drain electrode of said first NMOS transistor; and wherein the conducting circuit portion associated with said pull-down transistor stage further comprises a NMOS transistor having a gate electrode receiving the output signal of said second inverter, and a drain electrode and a source electrode respectively connected to the source electrode and drain electrode of said first PMOS transistor.