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EP0251275A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Noise cancelling circuit

Assignee: Toshiba Corp
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Filing: 1987-06-29
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Granted: —
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Expires: 2007-06-29
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Abstract

Abstract A noise cancelling circuit includes a delay circuit (19) for delaying an input signal which is supplied to an input terminal (18), and a signal processing circuit (Q1 to Q6, 23) responsive to the input signal and an output signal from the delay circuit (19), to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements (Q1 and Q3) connected in series between a first power supply terminal (Vcc) and an output (20), and a second switch­ing circuit, which includes third and fourth switching elements (Q2 and Q4) connected in series between a sec­ond power supply terminal and the output (20), wherein the first and third switching elements (Q1 and Q2) are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements (Q3 and Q4) are responsive to the output signal of the delay circuit (19), by which they too are set in mutually opposite conduction states.

Inventors

  • 👤 Tomotaka C/O Patent Division Saito
  • 👤 Kazumasa C/O Patent Division Ando
  • 👤 Akira Wada

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 06:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 165 words
A noise cancelling circuit comprising: delay means (19) for delaying an input signal which is supplied to an input terminal (18), and a signal pro­cessing circuit (Q1 to Q6, 23), responsive to the input signal and an output signal from the delay means (19), characterized in that said signal processing circuit comprises: a first switching circuit, including first and second switching means (Q1 and Q3) connected in series between a first power supply terminal (Vcc) and an out­put terminal (20) and a second switching circuit, including third and fourth switching means (Q2 and Q4) connected in series between a second power supply terminal and the output terminal (20) wherein said first and third switching means (Q1 and Q2) are responsive to said input signal, by which they are set in mutually opposite conduction states, and said second and fourth switching means (Q3 and Q4) are responsive to an output signal from the delay means (19), by which they are set in mutually opposite conduc­tion states.
Claim 2
Dependent Claim 165 words
A noise cancelling circuit comprising: delay means (19) for delaying an input signal which is supplied to an input terminal (18), and a signal pro­cessing circuit (Q1 to Q6, 23), responsive to the input signal and an output signal from the delay means (19), characterized in that said signal processing circuit comprises: a first switching circuit, including first and second switching means (Q1 and Q3) connected in series between a first power supply terminal (Vcc) and an out­put terminal (20) and a second switching circuit, including third and fourth switching means (Q2 and Q4) connected in series between a second power supply terminal and the output terminal (20) wherein said first and third switching means (Q1 and Q2) are responsive to said input signal, by which they are set in mutually opposite conduction states, and said second and fourth switching means (Q3 and Q4) are responsive to an output signal from the delay means (19), by which they are set in mutually opposite conduc­tion states.
Claim 3
Dependent Claim 89 words
A noise cancelling circuit according to claim 1, characterized in that: said first switching circuit includes first and second P-channel MOS transistors (Q1 and Q3) connected in series between said first power supply terminal (Vcc) and said output terminal (20), and respectively serving as said first and second switching means; and said second switching circuit includes first and second N-channel MOS transistors (Q2 and Q4) connected in series between said second power supply terminal and said output terminal (20), and respectively serving as said third and fourth switching means.
Claim 4
Dependent Claim 43 words
A noise cancelling circuit according to claim 1 or 2, characterized in that said signal processing circuit further includes a latch circuit (23) for latching a potential on a connection node between said first and second switching circuits (Q1, Q3 and Q2, Q4).
Claim 5
Dependent Claim 131 words
A noise cancelling circuit according to claim 1 or 2, characterized in that said signal pro­cessing circuit further includes: a fifth switching means (Q5), connected at one end to a connection node between said first and second switching means (Q1 and Q3), and at the other end to said output terminal (20), and responsive to said input signal, by which it is set in an opposite conduction state to that of said first switching means; and sixth switching means (Q6), connected at one end to a connection node between said third and fourth switching means (Q2 and Q4), and at the other end to said output terminal (20), and responsive to said input signal, by which it is set in the same conduction state as that of said first switching means.
Claim 6
Dependent Claim 27 words
A noise cancelling circuit according to claim 4, characterized in that said fifth and sixth switching means comprise N- and P-channel MOS transis­tors (Q5 and Q6), respectively.

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