System for controlling the number of data pieces in a queue memory

Claim 1

A system for controlling the number of data pieces in a queue memory, comprising: means for fetching an external instruction having a detectable number of data pieces and for providing an input information signal representing said detectable number; a memory for receiving and storing said external instruction and for providing an instruction having a particular number of data pieces; decoding means, receiving said instruction having said particular number of data pieces, for providing an output information signal representing said particular number; a counter for holding and updating a combined information signal representing a total number of data pieces presently stored in said memory, said counter further comprising: a plurality of means arranged in parallel, each responsive to said current value of said combined information signal for producing an adjusted information signal; selecting means, receiving said adjusted information signals and responsive to said second control signal, for providing a selected one of said adjusted information signals; and means for receiving and holding said selected adjusted information signal and for providing said selected adjusted information signal as said updated current value of said combined information signal; and control means, receiving said current value of said combined information signal and responsive to said input information signal and said output information signal, for providing a first control signal and a second control signal to said memory and said counter, respectively.

Claim 2

A system for controlling the number of data pieces in a queue memory, comprising: means for fetching an external instruction having a detectable number of data pieces and for providing an input information signal representing said detectable number; a memory for receiving and storing said external instruction and for providing an instruction having a particular number of data pieces; decoding means, receiving said instruction having said particular number of data pieces, for providing an output information signal representing said particular number; a counter for holding and updating a combined information signal representing a total number of data pieces presently stored in said memory, said counter further comprising: a plurality of means arranged in parallel, each responsive to said current value of said combined information signal for producing an adjusted information signal; selecting means, receiving said adjusted information signals and responsive to said second control signal, for providing a selected one of said adjusted information signals; and means for receiving and holding said selected adjusted information signal and for providing said selected adjusted information signal as said updated current value of said combined information signal; and control means, receiving said current value of said combined information signal and responsive to said input information signal and said output information signal, for providing a first control signal and a second control signal to said memory and said counter, respectively.

Claim 9

A system for controlling the number of data pieces in a queue memory, comprising: an instruction fetch section for fetching an external instruction and for detecting and outputting the number of data pieces in the instruction; memory means for storing a plurality of instructions successively output from said instruction fetch section, and for outputting said successive instruction on a first-in-first-out basis; an instruction decode section for detecting and outputting the number of data pieces in an instruction received from said memory means; a queue control section for controlling said memory means and for outputting control signals according to a difference between the number of data pieces output from said instruction fetch section and the number of data pieces output from said instruction decode section; n, n being a predetermined integer, incrementor circuits for adding 1, 2, 3, . . . and n to a current value, respectively, with said current value representing the effective number of data pieces currently stored in said memory means; n decrementer circuits for subtracting 1,2,3, . . . and n from said current value, respectively; a selector for selecting one circuit among said incrementor circuits and said decrementer circuits according to said control signals for outputting a result derived from the calculation by said selected one circuit on said current value; and a latch for outputting said result to said queue control section and to said incrementor circuits and said decrementer circuits as a new current value.

Claim 10

A system for controlling the number of data pieces in a queue memory, comprising: an instruction fetch section for fetching an external instruction and for detecting and outputting the number of data pieces in the instruction; memory means for storing a plurality of instructions successively output from said instruction fetch section, and for outputting said successive instruction on a first-in-first-out basis; an instruction decode section for detecting and outputting the number of data pieces in an instruction received from said memory means; a queue control section for controlling said memory means and for outputting control signals according to a difference between the number of data pieces output from said instruction fetch section and the number of data pieces output from said instruction decode section; n, n being a predetermined integer, incrementor circuits for adding 1, 2, 3, . . . and n to a current value, respectively, with said current value representing the effective number of data pieces currently stored in said memory means; n decrementer circuits for subtracting 1,2,3, . . . and n from said current value, respectively; a selector for selecting one circuit among said incrementor circuits and said decrementer circuits according to said control signals for outputting a result derived from the calculation by said selected one circuit on said current value; and a latch for outputting said result to said queue control section and to said incrementor circuits and said decrementer circuits as a new current value.