US4677545A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor having macro-rom and main program queues
Assignee: Nokia Bell Labs
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Filing: 1984-10-12
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Granted: 1987-06-30
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Expires: 2004-10-12
Abstract
Abstract A microprocessor with a macro-rom exhibits reduced latency time and greater flexibility by including both a macro-rom queue and a main program queue. The arrangement eliminates the undesirable latency associated with fetching program as part of a return sequence from a macro-rom instruction. Also, the arrangement allows parameters to be extracted from the main program queue as the macrosequence is executing from the macro-roms program queue.
Inventors
- 👤 Donald E. Blahut
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3824; G06F9/383
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
108 words
A microprocessor arrangement comprising a microprocessor portion together with first and second memories for respectively storing first and second program sequences of data, said microprocessor portion including first and second queues connected for receiving from said first and second memories said data of said first and second program sequences, respectively, and for delivering said data of said first and second sequences, respectively, to the microprocessor portion for processing by the microprocessor portion, and control means responsive to data constituting an instruction in said first program sequence for enabling said second queue to receive data of said second sequence from the second memory for processing by the microprocessor portion.
Claim 2
Dependent Claim
108 words
A microprocessor arrangement comprising a microprocessor portion together with first and second memories for respectively storing first and second program sequences of data, said microprocessor portion including first and second queues connected for receiving from said first and second memories said data of said first and second program sequences, respectively, and for delivering said data of said first and second sequences, respectively, to the microprocessor portion for processing by the microprocessor portion, and control means responsive to data constituting an instruction in said first program sequence for enabling said second queue to receive data of said second sequence from the second memory for processing by the microprocessor portion.
Claim 3
Dependent Claim
26 words
An arrangement in accordance with claim 1 wherein said microprocessor portion is integrated on a semiconductor chip and wherein said second memory comprises an on-chip memory.
Claim 4
Dependent Claim
15 words
A microprocessor arrangement in accordance with claim 2 wherein said on-chip memory comprises a macro-rom.
Claim 5
Dependent Claim
46 words
A microprocessor arrangement in accordance with claim 3 also including an output multiplexer connected to the outputs of said first and second queues and adapted for transmitting outputs from said first or second queues on a mutually exclusive basis under the control of said control means.
Claim 6
Dependent Claim
30 words
A microprocessor arrangement in accordance with claim 4 also including a byte align circuit connected to said output multiplexer to deliver aligned program data for processing by said microprocessor portion.
Claim 7
Dependent Claim
43 words
A microprocessor arrangement in accordance with claim 2 wherein said on-chip memory comprises a macro-rom, said microprocessor portion including means responsive to data constituting an instruction in said second program sequence for extracting data from said first program sequence in said first queue.
Claim 8
Dependent Claim
57 words
A microprocessor arrangement in accordance with claim 6 including means responsive to said data constituting said instruction in the second program sequence for disabling said macro-rom and said second queue from delivering data and for enabling said first queue to deliver data of said first program sequence to the microprocessor portion for processing by the microprocessor portion.
Claim 9
Dependent Claim
177 words
A microprocessor including a PLA and a macro-rom for cooperation with an external source of main program data sequences including a macro-instruction, said macro-rom storing macro-rom data sequences, first and second queues connected to said external source and said macro-rom, respectively, so as to receive data from said external source and from said macro-rom respectively and so as to deliver data from said first and second queues to the microprocessor for processing by the microprocessor, said PLA being responsive to said macro-instruction for selectively causing said macro-rom to deliver data to said second queue, means responsive to a first instruction in said macro-rom sequence for enabling said first queue to deliver data to the microprocessor for such processing and for thereafter enabling said second queue to resume delivering data to the microprocessor for such processing, and means responsive to a second instruction in said macro-rom sequence for disabling said macro-rom and said second queue from deliverng data and for enabling said first queue to deliver data of said main program sequence to the microprocessor for such processing.
Claim 10
Dependent Claim
177 words
A microprocessor including a PLA and a macro-rom for cooperation with an external source of main program data sequences including a macro-instruction, said macro-rom storing macro-rom data sequences, first and second queues connected to said external source and said macro-rom, respectively, so as to receive data from said external source and from said macro-rom respectively and so as to deliver data from said first and second queues to the microprocessor for processing by the microprocessor, said PLA being responsive to said macro-instruction for selectively causing said macro-rom to deliver data to said second queue, means responsive to a first instruction in said macro-rom sequence for enabling said first queue to deliver data to the microprocessor for such processing and for thereafter enabling said second queue to resume delivering data to the microprocessor for such processing, and means responsive to a second instruction in said macro-rom sequence for disabling said macro-rom and said second queue from deliverng data and for enabling said first queue to deliver data of said main program sequence to the microprocessor for such processing.
References Cited (Backward Citations)
US4278837A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |