Electrostatic discharge protection circuit with dynamic triggering

Claim 1

An electrostatic discharge (ESD) protection circuit comprising a bus diode-connected to at least one signal pad of an integrated circuit with an anode of a diode connected to the signal pad and a cathode of the diode connected to said bus, said bus also coupled to a positive-voltage power supply, a shunt element capable, when active, of delivering current from said bus to a ground plane of said integrated circuit, said shunt element activated by a trigger voltage applied thereto, triggering means responsive to a pad-to-ground voltage between said signal pad and said ground plane for providing said trigger voltage whenever said pad-to-ground voltage exceeds a threshold characteristic of an ESD event, said triggering means including a string of diode-connected field effect transistors (FETs) coupled between said signal pad and said ground plane with a node between two of said diode-connected FETs, a resistive-load inverter with a load resistor and an n-channel trigger FET connected in series between said bus and said ground plane, a gate of said trigger FET connected to said node of said string of diode-connected FETs, an output node of said resistive-load inverter being between said load resistor and said trigger FET, and a CMOS inverter with an input connected to said output node of said resistive-load inverter and with an output connected to said shunt element.