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US5305462A Expired / Lapsed US ⏱️ 0.0 years remaining

Mechanism for broadcasting data in a massively parallell array processing system

Assignee: Hewlett Packard Development Co LP
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Filing: 1993-06-03
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Granted: 1994-04-19
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Expires: 2013-06-03
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Abstract

Abstract An array processing system including a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing elements including an input multiplexer having a multiplexer output line and a plurality of multiplexer input lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; an output demultiplexer having a demultiplexer input line and a plurality of demultiplexer output lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; and a control circuit, which responds to a broadcast control signal by electrically coupling the input multiplexer output line in that processing element to the output demultiplexer input line in that processing element.

Inventors

  • 👤 Robert S. Grondalski

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023; G11; G11C; G11C29/00; G11C29/006

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 211 words
An array processing system comprising: a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing elements comprising an input multiplexer having a multiplexer output line and a plurality of multiplexer input lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; a demultiplexer circuit having a first input line and a plurality of first output lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element, said demultiplexer circuit comprising a control circuit that responds to a broadcast control signal by electrically coupling the output line of said input multiplexer of the same processing element to one or more of said first output lines to form a signal path from a selected one of the plurality of multiplexer input lines to said one or more first output lines, wherein said signal path is without any intermediate storage and/or latching devices that delay the propagation of a broadcast signal over said signal path from said selected one of the plurality of multiplexer input lines to said one or more first output lines.
Claim 2
Dependent Claim 211 words
An array processing system comprising: a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing elements comprising an input multiplexer having a multiplexer output line and a plurality of multiplexer input lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; a demultiplexer circuit having a first input line and a plurality of first output lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element, said demultiplexer circuit comprising a control circuit that responds to a broadcast control signal by electrically coupling the output line of said input multiplexer of the same processing element to one or more of said first output lines to form a signal path from a selected one of the plurality of multiplexer input lines to said one or more first output lines, wherein said signal path is without any intermediate storage and/or latching devices that delay the propagation of a broadcast signal over said signal path from said selected one of the plurality of multiplexer input lines to said one or more first output lines.
Claim 3
Dependent Claim 38 words
The array processing system of claim 1 wherein the processing elements of said grid array are arranged in rows and columns and wherein the group of nearest neighbor processing elements for any given processing element includes four members.
Claim 4
Dependent Claim 68 words
The array processing system of claim 2 wherein the four members of the group of nearest neighbors for said given processing element includes the two processing elements on either side of said given processing element in the row to which said given processing element belongs and the two processing elements one either side of said given processing element in the column to which said given processing element belongs.
Claim 5
Dependent Claim 29 words
The array processing system of claim 1 further comprising a system control circuit which generates a direction control signal that controls the operation of all of said input multiplexers.
Claim 6
Dependent Claim 44 words
The array processing system of claim 4 wherein the direction control signal determines for each processing element the particular member of the group of neighbor processing elements for that processing element from which that processing element will receive input data through its input multiplexer.
Claim 7
Dependent Claim 37 words
The array processing system of claim 4 wherein the direction control signal has at least four states each of which causes the input multiplexer in each processing element to select a different one of its input lines.
Claim 8
Dependent Claim 64 words
The array processing system of claim 1 wherein each of said processing elements further comprises a processing means which performs preselected operations on data sent to that processing means and a first multiplexer which in response to a neighbor mode signal completes a data transfer path for transferring data at the output of the input multiplexer into the processing means in that processing element.
Claim 9
Dependent Claim 91 words
The array processing system of claim 1 wherein each of said processing elements further comprises a processing means which performs preselected operations on data sent to that processing means and which places output data onto a data line and wherein said demultiplexer circuit includes a multiplexer which selects between the output line of the input multiplexer in the same processing element and the data line as a source of data that is to be sent to said one or more output lines of the demultiplexer circuit in the same processing element.
Claim 10
Dependent Claim 37 words
The array processing system of claim 1 wherein the demultiplexer circuit in each of said processing elements further comprises an output demultiplexer having an input line and having said plurality of output lines as its output lines.
Claim 11
Dependent Claim 38 words
The array processing system of claim 9 wherein the processing elements of said grid array are arranged in rows and columns and wherein the group of nearest neighbor processing elements for any given processing element includes four members.
Claim 12
Dependent Claim 68 words
The array processing system of claim 10 wherein the four members of the group of nearest neighbors for said given processing elements includes the two processing elements on either side of said given processing element in the row to which said given processing element belongs and the two processing elements on either side of said given processing element in the column to which said given processing element belongs.
Claim 13
Dependent Claim 35 words
The array processing system of claim 9 further comprising a system control circuit which generates a direction control signal that controls the operation of all of said input multiplexers and all of said output demultiplexer.
Claim 14
Dependent Claim 44 words
The array processing system of claim 12 wherein the direction control signal determines for each processing element the particular member of the group of neighbor processing elements for that processing element from which that processing element will receive input data through its input multiplexer.
Claim 15
Dependent Claim 44 words
The array processing system of claim 12 wherein the direction control signal determines for each processing element the particular member of the group of neighbor processing elements for that processing element to which that processing element will send output data through its output demultiplexer.
Claim 16
Dependent Claim 56 words
The array processing system of claim 12 wherein the direction control signal has at least four states each of which causes the input multiplexer in each processing element to select a different one of its input lines and which causes the output demultiplexer in each processing element to select a different one of its output lines.
Claim 17
Dependent Claim 64 words
The array processing system of claim 13 wherein each of said processing elements further comprises a processing means which performs preselected operations on data sent to that processing means and a first multiplexer which in response to a neighbor mode signal completes a data transfer path for transferring data at the output of the input multiplexer into the processing means in that processing element.
Claim 18
Dependent Claim 22 words
The array processing system of claim 16 wherein said output demultiplexer in each processing element is enabled by said neighbor mode signal.
Claim 19
Dependent Claim 85 words
The array processing system of claim 9 wherein each of said processing elements further comprises a processing means which performs preselected operations on data sent to that processing means and which places output data onto a data line and wherein said control circuit includes a second multiplexer which selects between the output line of the input multiplexer in the same processing element and the data line as a source of data that is to be sent to the output demultiplexer for the same processing element.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-18 1997-10-18 1998-04-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-18 2001-10-18 2002-04-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-18 2005-10-18 2006-04-19 $7700.00 Window Closed / Lapsed

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