US4396979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor with improved arithmetic logic unit data path
Assignee: National Semiconductor Corp
•
Filing: 1980-05-30
•
Granted: 1983-08-02
•
Expires: 2000-05-30
Abstract
Abstract A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.
Inventors
- 👤 Yeshayahu Mor
- 👤 Allan M. Schiffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F12/00; G06F12/14; G06F13/00; G06F13/14; G06F13/36; G06F21/00; G06F21/70; G06F21/71; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30032; G06F9/30098; G06F9/30101; G06F9/30105; G06F9/30112; G06F2207/00; G06F2207/72; G06F2207/7219
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
75 words
A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprising: an arithmetic logic unit having a first and a second input and an output; a plurality of register means, at least one of which is a bi-directionally shifting register means; and means for selectively coupling each of said plurality of register means to said first and said second inputs and said output of said arithmetic logic unit.
Claim 2
Dependent Claim
75 words
A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprising: an arithmetic logic unit having a first and a second input and an output; a plurality of register means, at least one of which is a bi-directionally shifting register means; and means for selectively coupling each of said plurality of register means to said first and said second inputs and said output of said arithmetic logic unit.
Claim 3
Dependent Claim
63 words
The microprocessor of claim 1 comprising: means for repeating an arithmetic logic unit operation and a bi-directionally shifting register means operation and wherein at least one other of said plurality of register means comprises a counting means; and means coupled to said counting means for controlling the number of repetitions of said arithmetic logic unit operation and said bi-directionally shifting register means operation.
Claim 4
Dependent Claim
32 words
The microprocessor of claim 2 comprising: a shifter; and means for coupling said shifter to said output of said arithmetic logic unit and to an input of said plurality of register means.
References Cited (Backward Citations)
US4106090A
Cited
US4301505A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |