US5119484A
Expired / Lapsed
US
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Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-07-25
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Granted: 1992-06-02
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Expires: 2009-07-25
Abstract
Abstract A processor for use in a digital data processing system includes a data path which, in the execution of a program instruction, processes generally a series microinstructions from a control circuit. In some cases, the operation to be performed by the data path depends on the results of a previous operation. The data path includes a circuit which generates preset operation codes and a multiplexer which, during those cases, enables either the microinstructions from the control circuit or the preset operation code depending on the results of the previous operation.
Inventors
- 👤 T. Francis Fox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/267
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
A processor for use in a digital data processing system, comprising: A. an arithmetic and logic unit for responding to operational control words applied to a control terminal thereof by performing operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; B. control means for generating a series of control words in response to program instructions and in a format that enables said arithmetic and logic unit to respond directly thereto; C. means for providing at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and D. control word selection means connected to said control means, said means for providing said alternate control word, and said control terminal of said arithmetic and logic unit for selectively coupling either the control word or the alternate control word to said control terminal as one of said operational control words in response to said processed data signals at said output terminal and the program instruction that caused said control means to generate said control word.
Claim 2
Dependent Claim
184 words
A processor for use in a digital data processing system, comprising: A. an arithmetic and logic unit for responding to operational control words applied to a control terminal thereof by performing operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; B. control means for generating a series of control words in response to program instructions and in a format that enables said arithmetic and logic unit to respond directly thereto; C. means for providing at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and D. control word selection means connected to said control means, said means for providing said alternate control word, and said control terminal of said arithmetic and logic unit for selectively coupling either the control word or the alternate control word to said control terminal as one of said operational control words in response to said processed data signals at said output terminal and the program instruction that caused said control means to generate said control word.
Claim 3
Dependent Claim
89 words
A processor as defined in claim 1 wherein said control word selection means comprises: A. multiplexer means connected to said control word generating means and said means for providing said alternate control word for selectively coupling either the control word or the alternate control word to said control terminal as one of said operational control words in response to a multiplexer control signal; B. multiplexer control means for generating said multiplexer control signal in response to a said program instruction and the processed data signals at said output terminal.
Claim 4
Dependent Claim
59 words
A processor as defined in claim 2 in which said multiplexer control means comprises: A. program instruction identifier means for generating program instruction identification signals in response to predetermined ones of said program instructions; and B. multiplexer control circuit means for generating said multiplexer control signal in response to said program instruction identification signals and said processed data signals.
Claim 5
Dependent Claim
226 words
A processor for use in a digital data processing system of the kind in which processing occurs in successive processing cycles, said processor comprising: A. an arithmetic and logic unit for responding to operational control words applied to a control terminal thereof by performing, during each processing cycle, operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; B. control means for generating, in a plurality of successive processing cycles, a series of control words in response to program instructions and in a format that enables said arithmetic and logic unit to respond directly thereto; C. means for providing, during at least some of said processing cycles, at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and D. control word selection means connected to said control means, said means for providing said alternate control word, and said control terminal of said arithmetic and logic unit for selectively coupling, during each processing cycle, either the control word generated by said control means in response to one of said instructions during said cycle or the alternate control word to said control terminal as one of said operational control words in response to said processed data signals at said output terminal and said one program instruction.
Claim 6
Dependent Claim
226 words
A processor for use in a digital data processing system of the kind in which processing occurs in successive processing cycles, said processor comprising: A. an arithmetic and logic unit for responding to operational control words applied to a control terminal thereof by performing, during each processing cycle, operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; B. control means for generating, in a plurality of successive processing cycles, a series of control words in response to program instructions and in a format that enables said arithmetic and logic unit to respond directly thereto; C. means for providing, during at least some of said processing cycles, at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and D. control word selection means connected to said control means, said means for providing said alternate control word, and said control terminal of said arithmetic and logic unit for selectively coupling, during each processing cycle, either the control word generated by said control means in response to one of said instructions during said cycle or the alternate control word to said control terminal as one of said operational control words in response to said processed data signals at said output terminal and said one program instruction.
Claim 7
Dependent Claim
93 words
A processor as defined in claim 4 wherein said control word selection means comprises: A. multiplexer means connected to said control word generating means and said means for providing said alternate control word for selectively coupling either the control word or the alternate control word to said control terminal as one of said operational control words in response to a multiplexer control signal; B. multiplexer control means for generating said multiplexer control signal, during each processing cycle, in response to a said program instruction and the processed data signals at said output terminal.
Claim 8
Dependent Claim
63 words
A processor as defined in claim 5 in which said multiplexer control means comprises: A. program instruction identifier means for generating program instruction identification signals in response to predetermined ones of said program instructions; and B. multiplexer control circuit means for generating said multiplexer control signal, during each processing cycle in response to said program instruction identification signals and said processed data signals.
Claim 9
Independent Claim
185 words
A method of processing data in a digital data processing system comprising: providing an arithmetic and logic unit that responds to operational control words applied to a control terminal thereof by performing operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; generating, in response to program instructions, a series of control words in a format that enables said arithmetic and logic unit to respond directly thereto; providing at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and responding to said processed data signals from a said operation performed by said arithmetic and logic unit and to one of said program instructions by selectively applying either the control word generated by said control means in response to said one instruction or the alternate control word to the arithmetic and logic unit as one of said operational control words, said arithmetic and logic unit performing a subsequent operation in response to said one operational control word to generate additional said processed data signals.
Claim 10
Independent Claim
185 words
A method of processing data in a digital data processing system comprising: providing an arithmetic and logic unit that responds to operational control words applied to a control terminal thereof by performing operations on input data signals applied to input terminals thereof and generating processed data signals at an output terminal of said unit; generating, in response to program instructions, a series of control words in a format that enables said arithmetic and logic unit to respond directly thereto; providing at least one alternate control word in a format that enables said arithmetic and logic unit to respond directly thereto; and responding to said processed data signals from a said operation performed by said arithmetic and logic unit and to one of said program instructions by selectively applying either the control word generated by said control means in response to said one instruction or the alternate control word to the arithmetic and logic unit as one of said operational control words, said arithmetic and logic unit performing a subsequent operation in response to said one operational control word to generate additional said processed data signals.
Claim 11
Dependent Claim
52 words
The method of claim 7 wherein said step of selectively applying includes multiplexing between said control word and said alternate control word in response to a multiplexer control signal, and further comprising generating said multiplexer control signal in response to the program instruction and the processed data signals at said output terminal.
Claim 12
Dependent Claim
48 words
The method of claim 8 wherein said step of generating said multiplexer control signal includes generating program instruction identification signals in response to predetermined ones of said program instructions and generating the multiplexer control signal in response to the program instruction identification signals and the processed data signals.
References Cited (Backward Citations)
US3766532A
Cited
US4168523A
Cited
US4298927A
Cited
US4300193A
Cited
CA1139450A
Cited
JPS5730196A
Cited
US4463419A
Cited
US4785393A
Cited
WO1986005015A1
Cited
US4773002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-02 | 1995-12-02 | 1996-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-02 | 1999-12-02 | 2000-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-02 | 2003-12-02 | 2004-06-02 | $7700.00 | Window Closed / Lapsed |