Patent US5305283A successfully refreshed from Google Patents.
US5305283A
Expired / Lapsed
US
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Dram column address latching technique
Assignee: Nvidia Corp
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Filing: 1991-04-05
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Granted: 1994-04-19
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Expires: 2011-04-05
Abstract
Abstract Apparatus and a method for latching a column address in a DRAM, having increased speed and no race conditions. The method is comprised of the steps of receiving column select and column address input signals, enabling detection and indication, by generation of an indication signal, of the presence of each stable column address input signal upon the presence of a column select signal, summing the indication signals, and operating a latch by each of the column address input signals whereby a DRAM column can be addressed upon enabling by the summed indication signals, whereby the latching is not enabled without a first indication of the presence of a stable column address and whereby the first indication is prevented without the earlier presence of a column select signal.
Inventors
- 👤 Gregg M. Shimokura
- 👤 Peter B. Gillingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:47
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; G11C11/4087; G11C8/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns comprising: (a) means for receiving DRAM column select and column address input signals, (b) means for enabling detection and indication, by generating an indication signal, of the presence of each column address input signal, in the presence of a column select signal, (c) means for logically ANDing said indication signals to provide logic signals, and (d) means for latching each of said column address input signals by said logic signals whereby a DRAM column can be addressed upon enabling by said logic signals.
Claim 2
Dependent Claim
111 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns comprising: (a) means for receiving DRAM column select and column address input signals, (b) means for enabling detection and indication, by generating an indication signal, of the presence of each column address input signal, in the presence of a column select signal, (c) means for logically ANDing said indication signals to provide logic signals, and (d) means for latching each of said column address input signals by said logic signals whereby a DRAM column can be addressed upon enabling by said logic signals.
Claim 3
Dependent Claim
211 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns whereby at least one memory cell of a row of memory cells can be read or written, comprising: (a) column address signal inputs, (b) column address latches each connected to one of said inputs for receiving column address signals and outputting a column enable signal, (c) address transition detection circuits each having an input connected to one of said inputs for receiving said column address signals, for detecting address signal inputs and outputting "address present" confirmation (ATD) signals, (d) a chip select (/CAS) signal input connected to enable inputs of each of said address transition detection circuits, and (e) an AND gate having inputs connected to the outputs of said address transition detection circuits for receiving said ATD signals and having an output connected to enable inputs of said latches, whereby upon receipt of a new column address input signal, latching thereof into a corresponding column address latch is not enabled to store said new column address input signal until a /CAS signal has charged to a level enabling said address transition detection circuitry to receive and detect said new address input signal.
Claim 4
Dependent Claim
211 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns whereby at least one memory cell of a row of memory cells can be read or written, comprising: (a) column address signal inputs, (b) column address latches each connected to one of said inputs for receiving column address signals and outputting a column enable signal, (c) address transition detection circuits each having an input connected to one of said inputs for receiving said column address signals, for detecting address signal inputs and outputting "address present" confirmation (ATD) signals, (d) a chip select (/CAS) signal input connected to enable inputs of each of said address transition detection circuits, and (e) an AND gate having inputs connected to the outputs of said address transition detection circuits for receiving said ATD signals and having an output connected to enable inputs of said latches, whereby upon receipt of a new column address input signal, latching thereof into a corresponding column address latch is not enabled to store said new column address input signal until a /CAS signal has charged to a level enabling said address transition detection circuitry to receive and detect said new address input signal.
Claim 5
Independent Claim
137 words
A method of addressing columns in a dynamic random access memory (DRAM) comprising the steps of: (a) receiving column select and column address input signals, (b) enabling detection and indication by generation of an indication signal of the presence of each stable column address input signal, upon the presence of a column select signal, (c) summing said indication signals, (d) enabling a corresponding latch by each of said indication signals, to latch corresponding ones of said column address input signals, (e) addressing a DRAM column using said latched address input signals upon enabling of a column decode control by said summed indication signals, whereby said latching is not enabled without a first indication of the presence of a stable column address and whereby said first indication is prevented without the earlier presence of a column select signal.
Claim 6
Independent Claim
137 words
A method of addressing columns in a dynamic random access memory (DRAM) comprising the steps of: (a) receiving column select and column address input signals, (b) enabling detection and indication by generation of an indication signal of the presence of each stable column address input signal, upon the presence of a column select signal, (c) summing said indication signals, (d) enabling a corresponding latch by each of said indication signals, to latch corresponding ones of said column address input signals, (e) addressing a DRAM column using said latched address input signals upon enabling of a column decode control by said summed indication signals, whereby said latching is not enabled without a first indication of the presence of a stable column address and whereby said first indication is prevented without the earlier presence of a column select signal.
Claim 7
Dependent Claim
219 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns whereby at least one memory cell of a row of memory cells can be read or written, comprising: (a) column address signal inputs, (b) column address latches each connected to one of said inputs for receiving column address signals and outputting a column enable signal, (c) address transition detection circuits each having an input connected to one of said inputs for receiving said column address signals, for detecting address signal inputs and outputting "address present" confirmation (ATD) signals, (d) a chip select (/CAS) signal input connected to enable inputs of each of said address transition detection circuits, (e) an AND gate having inputs connected to the outputs of said address transition detection circuits for receiving said ATD signals, and (f) enable inputs of each of said latches connected to an output of a corresponding column address detection circuit, whereby upon receipt of a new column address input signal, latching thereof into a corresponding column address latch is not enabled to store said new column address input signal until a /CAS signal has changed to a level enabling said address transition detection circuitry to receive and detect said new address input signal.
Claim 8
Dependent Claim
219 words
A dynamic random access memory (DRAM) having row lines (rows) and column lines (columns), memory cells associated with the rows and columns, and means for addressing the columns whereby at least one memory cell of a row of memory cells can be read or written, comprising: (a) column address signal inputs, (b) column address latches each connected to one of said inputs for receiving column address signals and outputting a column enable signal, (c) address transition detection circuits each having an input connected to one of said inputs for receiving said column address signals, for detecting address signal inputs and outputting "address present" confirmation (ATD) signals, (d) a chip select (/CAS) signal input connected to enable inputs of each of said address transition detection circuits, (e) an AND gate having inputs connected to the outputs of said address transition detection circuits for receiving said ATD signals, and (f) enable inputs of each of said latches connected to an output of a corresponding column address detection circuit, whereby upon receipt of a new column address input signal, latching thereof into a corresponding column address latch is not enabled to store said new column address input signal until a /CAS signal has changed to a level enabling said address transition detection circuitry to receive and detect said new address input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |