Look ahead high speed circuitry

Claim 2

The combination comprising: first and second power terminals for the application thereto of first and second voltages, respectively; an output point; first and second transistors, each transistor having a conduction path and a control electrode, means connecting the conduction path of said first transistor between said first power terminal and said output point; means connecting the conduction path of said second transistor between said output point and said second power terminal; a first means coupled to the control electrodes of said first and second transistors for, selectively, turning either one of them on and the other one off and for, selectively, turning them both off; and second means coupled to the control electrodes of said first and second transistors for, selectively, turning them both on and charging said output point to a level intermediate the voltages applied to said first and second power terminals.

Claim 3

The combination as claimed in claim 1, wherein said first means includes a signal input port, and also includes a first signal propagation path coupled between said signal input port and the control electrode of said first transistor and a second signal propagation path coupled between said signal input port and the control electrode of said second transistor; and wherein said second means includes third and fourth transistors, each transistor having first and second electrodes defining the ends of its conduction path and a control electrode; wherein the conduction path of said third transistor is connected between the control electrode of said first transistor and said output point; and wherein the conduction path of said fourth transistor is connected between the control electrode of said second transistor and said output point.

Claim 4

The combination as claimed in claim 2 wherein said second means includes a signal input terminal, and a pulse forming network having an input connected to said signal input terminal and having an output coupled to the control electrodes of said third and fourth transistors for either turning them both on or both off.

Claim 5

The combination as claimed in claim 2 wherein said first signal propagation path includes a first inverter connected at its output to the control electrode of said first transistor, wherein said second signal propagation path includes a second inverter connected at its output to the control electrode of said second transistor; and wherein the switching point of said first and second inverters is offset in a direction to enable the quick turn-on of said first and second transistors and the relatively slow turn off of these transistors, in response to signals applied to the input of said first and second inverters.

Claim 6

The combination as claimed in claim 4 wherein said first and fourth transistors are of one conductivity type and said second and third transistors are of opposite conductivity type to said one conductivity type; wherein said first and second inverters are complementary inverters, each being comprised of one transistor of said one conductivity type and another transistor of said opposite conductivity type; wherein the one transistor of said first inverter is smaller than, and of significantly greater impedance than, said other transistor of said first inverter; and wherein the one transistor of said second inverter is larger than, and of significantly lower impedance than, said another transistor of said second inverter.

Claim 7

The combination as claimed in claim 5 wherein said input point is adapted to receive a data signal and a first control signal; wherein said first signal path includes a first logic gate for coupling the signals at said input port to the input of said first inverter; and wherein said second signal path includes a second logic gate for coupling the signals at said input port to the input of said second inverter.

Claim 8

In a circuit to which is applied binary valued data input signals and in which the conduction path of a first pull-up transistor is connected between a first voltage terminal and an output point and in which the conduction path of a second pull-down transistor is connected between the output and a second voltage terminal, one of said first and second transistors being turned-on and the other one turned-off for one value of input signal and said one of said first and second transistors being turned-off and the other one turned-on for the other value of input signal, and said circuit being of the type to which is applied a second signal indicative that a new data signal is about to be applied to the circuit, the improvement comprising: normally non-conductive means connected to the control electrodes of said first and second transistors responsive to said second signal for momentarily turning-on both said first and second transistors and charging said output point to a voltage having a value intermediate the voltages applied to said first and second voltage terminals.

Claim 9

In a circuit to which is applied binary valued data input signals and in which the conduction path of a first pull-up transistor is connected between a first voltage terminal and an output point and in which the conduction path of a second pull-down transistor is connected between the output and a second voltage terminal, one of said first and second transistors being turned-on and the other one turned-off for one value of input signal and said one of said first and second transistors being turned-off and the other one turned-on for the other value of input signal, and said circuit being of the type to which is applied a second signal indicative that a new data signal is about to be applied to the circuit, the improvement comprising: normally non-conductive means connected to the control electrodes of said first and second transistors responsive to said second signal for momentarily turning-on both said first and second transistors and charging said output point to a voltage having a value intermediate the voltages applied to said first and second voltage terminals.

Claim 10

In a memory system in which a binary valued data signal is to be propagated via a circuit to which is applied first and second control signals prior to the application of the data signal to be propagated, said circuit comprising: first and second power terminals for the application thereto of first and second voltages, respectively; an output point; first and second transistors, each transistor having a conduction path and a control electrode, means connecting the conduction path of said first transistor between said first power terminal and said output point; means connecting the conduction path of said second transistor between said output point and said second power terminal; first means, responsive to said data input signal and to said first control signal, coupled to the control electrodes of said first and second transistors for, in the absence of said first control signal, turning one of them on and the other one off for one binary value of input signal and turning said one of them off and said other one on for the other value of input signal, and for, in the presence of said first control signal, normally turning off both said first and second transistors; and second means responsive to said second control signal coupled to the control electrodes of said first and second transistors for momentarily turning them both on and charging said output point to a level intermediate the voltages applied to said first and second power terminals prior to the application of a data signal to either one of the control electrodes of said first and second transistors.

Claim 11

In a memory system in which a binary valued data signal is to be propagated via a circuit to which is applied first and second control signals prior to the application of the data signal to be propagated, said circuit comprising: first and second power terminals for the application thereto of first and second voltages, respectively; an output point; first and second transistors, each transistor having a conduction path and a control electrode, means connecting the conduction path of said first transistor between said first power terminal and said output point; means connecting the conduction path of said second transistor between said output point and said second power terminal; first means, responsive to said data input signal and to said first control signal, coupled to the control electrodes of said first and second transistors for, in the absence of said first control signal, turning one of them on and the other one off for one binary value of input signal and turning said one of them off and said other one on for the other value of input signal, and for, in the presence of said first control signal, normally turning off both said first and second transistors; and second means responsive to said second control signal coupled to the control electrodes of said first and second transistors for momentarily turning them both on and charging said output point to a level intermediate the voltages applied to said first and second power terminals prior to the application of a data signal to either one of the control electrodes of said first and second transistors.

Claim 12

The combination as claimed in claim 8 wherein said second means includes third and fourth transistors; each transistor having a conduction path and a control electrode; wherein the conduction path of said third transistor is connected between the control electrode of said first transistor and said output point; wherein the conduction path of said fourth transistor is connected between the control electrode of said second transistor and said output point; and wherein said second means further includes a pulse forming network responsive to said second signal for turning-on both of said third and fourth transistors in response to a given condition of said second control signal.

Claim 13

The combination as claimed in claim 9: wherein said first, second, third and fourth transistors are insulated-gate field-effect transistors (IGFETs); wherein said first and fourth transistors are of one conductivity type; wherein said second and third transistors are of opposite conductivity type to said one conductivity type; and wherein said third and fourth transistors when turned-on conduct in the follower mode.

Claim 14

The combination as claimed in claim 8 wherein said first means includes a first signal propagation path coupled between said control electrode of said first transistor and an input port to which is applied said data input and said first control signal, and a second signal propagation path coupled between said control electrode of said second transistor and said input port; and wherein each one of said first and second paths propagates faster a signal tending to turn-on its associated transistor than a signal tending to turn-off its associated transistor.

Claim 15

The combination comprising: first and second power terminals for the application thereto of first and second voltages, respectively; an output point; first and second transistors, each transistor having a conduction path and a control electrode; means connecting the conduction path of said first transistor between said first power terminal and said output point; means connecting the conduction path of said second transistor between said output point and said second power terminal; means, coupled to the control electrodes of said first and second transistors for, selectively, turning either one of them on and the other one off; for, selectively, turning them both off; and for, selectively, turning them both on and charging said output point to a level intermediate the voltages applied to said first and second power terminals.

Claim 16

The combination comprising: first and second power terminals for the application thereto of first and second voltages, respectively; an output point; first and second transistors, each transistor having a conduction path and a control electrode; means connecting the conduction path of said first transistor between said first power terminal and said output point; means connecting the conduction path of said second transistor between said output point and said second power terminal; means, coupled to the control electrodes of said first and second transistors for, selectively, turning either one of them on and the other one off; for, selectively, turning them both off; and for, selectively, turning them both on and charging said output point to a level intermediate the voltages applied to said first and second power terminals.

Claim 17

The combination as claimed in claim 12 wherein said means includes a first means which includes a signal input port and also includes a first signal propagation path coupled between said signal input port and the control electrode of said first transistor and a second signal propagation path coupled between said signal input port and the control electrode of said second transistor; and wherein said means also includes a second means which includes a first selectively enabled conduction path means connected between the control electrode of said first transistor and said output point; and a second selectively enabled conduction path means connected between the control electrode of said second transistor and said output point.