US3845328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tri-state logic circuit
Assignee: RCA Corp
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Filing: 1973-02-12
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Granted: 1974-10-29
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Expires: 1993-02-12
Abstract
Abstract A first pair of complementary transistors have their conduction paths serially connected between supply and ground with the midpoint of the series connected to an output terminal. A control circuit comprising two pair of complementary transistors coupled to the control electrodes of the first pair of complementary transistors applies complementary signals thereto in response to a control signal manifestation of one value for maintaining both transistors of the first pair off, and applies identical signals thereto in response to a control signal manifestation of a second value for turning one transistor of the first pair on.
Inventors
- 👤 R Hollingsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:11
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
In combination: first and second circuit points across which an operating potential may be applied; first and second control terminals for receiving complementary binary valued control signals; a circuit output terminal; three pair of complementary transistors, each transistor having a conduction path and a control electrode, the conduction paths of the first pair being connected in series between said first and second circuit points and the midpoint of the series connected paths connected to said circuit output terminal, the conduction paths of the second pair being connected in series between said first circuit point and said first control terminal with the midpoint of the series connected paths connected to the control eleCtrode of one transistor of the first pair, the conduction paths of the third pair being connected in series between said second circuit point and said second control terminal with the midpoint of the series connected paths connected to the control electrode of the other transistor of said first pair; and a circuit input terminal connected to the control electrode of each transistor of the second and third pair of transistors.
Claim 2
Dependent Claim
182 words
In combination: first and second circuit points across which an operating potential may be applied; first and second control terminals for receiving complementary binary valued control signals; a circuit output terminal; three pair of complementary transistors, each transistor having a conduction path and a control electrode, the conduction paths of the first pair being connected in series between said first and second circuit points and the midpoint of the series connected paths connected to said circuit output terminal, the conduction paths of the second pair being connected in series between said first circuit point and said first control terminal with the midpoint of the series connected paths connected to the control eleCtrode of one transistor of the first pair, the conduction paths of the third pair being connected in series between said second circuit point and said second control terminal with the midpoint of the series connected paths connected to the control electrode of the other transistor of said first pair; and a circuit input terminal connected to the control electrode of each transistor of the second and third pair of transistors.
Claim 3
Dependent Claim
77 words
The combination recited in claim 1 further including: a fourth pair of complementary transistors, each transistor having a control electrode coupled to said first control terminal, one transistor having its conduction path coupled between said second control terminal and said first circuit point, the other transistor having one end of its conduction path coupled to said second circuit point; and means for applying a potential to the other end of the conduction path of said other transistor.
Claim 4
Dependent Claim
36 words
The circuit recited in claim 2 wherein said means for applying a potential to said other end of the conduction path of said other transistor comprises means coupling said other end to said second control terminal.
Claim 5
Dependent Claim
47 words
The circuit recited in claim 2 wherein said means for applying a potential to said other end of the conduction path of said other transistor, comprises means coupling said other end to said midpoint of the series connected conduction paths of said third pair of complementary transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-28 | 1978-04-29 | 1978-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-28 | 1982-04-29 | 1982-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-28 | 1986-04-29 | 1986-10-29 | $7700.00 | Window Closed / Lapsed |