Non-bus request refresh system for shortening refresh timing

Claim 2

In a computer including a CPU, a bus, a bus controller, one or more address signals, and a memory, where data is transferred between the CPU and memory via the bus during a CPU bus cycle, and where the beginning of the CPU bus cycle and type of CPU bus cycle is signalled by the CPU asserting a status signal which is transferred to the bus controller and the end of the CPU bus cycle is signalled by resetting a first signal, and where the requirement of a memory refersh operation is signalled by setting a second signal, first latching means coupled to said status signal and said bus controller for latching and transferring said status signal to said bus controller, and second latching means coupled to said address signals and said bus controller for latching and transferring said address signals to said bus controller, an improved method for refershing memory comprising the steps of: detecting the setting of the second signal when a memory refreshing memory comprising the steps of: detecting the setting of the second signal when a memory refresh operation is required; starting a memory refresh operation when the first signal is reset, to indicate that a CPU bus cycle has been completed, subsequent to the detection of the setting of said second signal; detecting the assertion of the status signal during said started memory refresh operation if the CPU initiates a new CPU bus cycle during said started refresh operation; latching the status signal in the first latching means after a first interval subsequent to the detection of the assertion of the status signal; latching the address signals in the second latching means after a second interval subsequent to the detection of the assertion of the status signal; transferring said latched status and address signals to the bus controller when said started refresh operation is completed to start a delayed CPU bus cycle; and delaying the resetting of said first signal until said started refresh operation and said delayed CPU bus cycle is completed.

Claim 3

The system as set forth in claim 1, wherein the step of latching the address signals is performed after the step of latching the status signal.

Claim 4

In a computer including a CPU, a bus, a bus controller having a status signal input, a memory address latch, and a memory, where data is transferred between the CPU and memory via the bus during a CPU bus cycle, and where the beginning of the CPU bus cycle and type of CPU bus cycle is signalled by the CPU asserting a status signal which is transferred to the bus controller and address signals which are transferred to the memory address latch and the end of the CPU bus cycle is signalled by resetting a first signal, and where the requirement of a memory refresh operation is signalled by setting a second signal, an improved system for refreshing memory comprising: a first latch having a data input that receives the status signal from the CPU, a latch input that receives a first latch signal, an output enable input that receives an output enable signal, and a data output, said first latch for latching said received status signal when said first latch signal is set and for outputting said latched status signal when said output enable signal is reset; a multiplexer having a first input for receiving the status signals from the CPU, a second input coupled to the data output of said first latch, a select input for receiving a select signal and an output that couples the bus controller status signal input to the first input when said select signal is reset and to the second input when said select signal is set: a second latch having a data input that receives the address signals from the CPU, a latch input that receives a second latch signal, an output enable input that receives an output enable signal, and a data output, said second latch for latching said received address signals when said second latch signal is set and for outputting said latched address signals when said output enable signal is reset; means, having an output enable input that receives said output enable signal, for providing a refresh address when said output enable signal is set; means for setting said output enable signal and for setting said select signal to start a refresh operation when said first signal is set subsequent to the setting of said second signal: means for setting said first and second latch signals to store the status and latch signals if the CPU asserts the status signals during said refresh operation to signal the beginning of a new CPU bus cycle; means for resetting said output enable signal when said started refresh operation is finished to transfer said latched status signal to the bus controller and said latched address signals to the address latch to start a delayed CPU bus cycle: and means for delaying resetting said third signal until said refresh operation and said delayed CPU bus cycle are completed.

Claim 5

In a computer including a CPU, a bus, a bus controller having a status signal input, a memory address latch, and a memory, where data is transferred between the CPU and memory via the bus during a CPU bus cycle, and where the beginning of the CPU bus cycle and type of CPU bus cycle is signalled by the CPU asserting a status signal which is transferred to the bus controller and address signals which are transferred to the memory address latch and the end of the CPU bus cycle is signalled by resetting a first signal, and where the requirement of a memory refresh operation is signalled by setting a second signal, an improved system for refreshing memory comprising: a first latch having a data input that receives the status signal from the CPU, a latch input that receives a first latch signal, an output enable input that receives an output enable signal, and a data output, said first latch for latching said received status signal when said first latch signal is set and for outputting said latched status signal when said output enable signal is reset; a multiplexer having a first input for receiving the status signals from the CPU, a second input coupled to the data output of said first latch, a select input for receiving a select signal and an output that couples the bus controller status signal input to the first input when said select signal is reset and to the second input when said select signal is set: a second latch having a data input that receives the address signals from the CPU, a latch input that receives a second latch signal, an output enable input that receives an output enable signal, and a data output, said second latch for latching said received address signals when said second latch signal is set and for outputting said latched address signals when said output enable signal is reset; means, having an output enable input that receives said output enable signal, for providing a refresh address when said output enable signal is set; means for setting said output enable signal and for setting said select signal to start a refresh operation when said first signal is set subsequent to the setting of said second signal: means for setting said first and second latch signals to store the status and latch signals if the CPU asserts the status signals during said refresh operation to signal the beginning of a new CPU bus cycle; means for resetting said output enable signal when said started refresh operation is finished to transfer said latched status signal to the bus controller and said latched address signals to the address latch to start a delayed CPU bus cycle: and means for delaying resetting said third signal until said refresh operation and said delayed CPU bus cycle are completed.