Method and apparatus for expanding a backplane interconnecting bus in a multiprocessor computer system without additional byte select signals

Claim 1

An expanded multiprocessor interconnection architecture having a common backplane bus, said expanded architecture being derived from a first architecture having a first data bus bit-width and a number of byte select control lines, said common backplane bus of said expanded architecture having an expanded data bus bit-width greater than said first data bus bit-width of said first architecture, and having the same number of byte select control lines as said first architecture, said backplane bus of said expanded architecture configured to operate with master and slave devices designed to utilize said expanded data bus bit-width of said expanded architecture, said backplane bus of said expanded architecture further configured to also operate with master and slave devices which are designed to utilize said first architecture without modification to the master and slave devices which are designed to utilize said first architecture, said expanded architecture comprising: a master request line coupled to master and slave devices designed to utilize the expanded bit-width of the expanded architecture, said master request line activated only by a master device designed to utilize the expanded architecture to indicate that the master device is attempting to initiate a transfer utilizing the expanded data bus bit-width; and a slave acknowledge response line coupled to master and slave devices designed to utilize the expanded data bus bit-width, said slave acknowledge response line activated only by a slave device designed to utilize the expanded data bus bit-width in response to an active signal n said master request line, said slave acknowledge line activated to indicate that the slave device is designed to utilize the entire bit-width of the expanded backplane architecture, and wherein the bit-width for each data transfer from said master device to a slave device conforming to either said first architecture or said expanded architecture is controlled in accordance with the signal provided on said slave acknowledge response line so that said expanded architecture does not require more byte select control lines than said first architecture.

Claim 8

A method of expanding a data bus width of a first multiprocessor interconnection architecture having a number of data lines comprising a first bit-width and a backplane bus with a plurality of byte select lines sufficient to indicate which bytes on the data bus are active during a bus transaction cycle to create a second expanded multiprocessor interconnection architecture with an expanded bit-width and with the same plurality of byte select control lines, said method comprising the steps of: increasing the number of data lines of said first multiprocessor interconnection architecture to provide a second number of data lines in said second expanded multiprocessor interconnection architecture; providing a master request interconnection line between master and slave devices designed to utilize the expanded bit-width of the second expanded architecture, said master request line carrying a master request signal activated only by a master device designed to utilize the entire bit-width of the second expanded architecture, said master request signal indicating that the master device is attempting to initiate a transfer utilizing the entire bit-width of the second expanded architecture; providing a slave response interconnection line between master and slave devices designed to utilize the expanded bit-width of the second expanded architecture, said slave response line carrying a slave response signal activated only by a slave device designed to utilize the entire bit-width of the second expanded architecture in response to an active master request signal on said master request line, said slave response signal indicating that the slave device is designed to utilize the bit-width of the second expanded architecture; and selectively controlling the bit-width of data transferred by said master to a slave device conforming to either said first architecture or said expanded architecture in accordance with said slave response signal such that said expanded architecture does not require more byte select control lines than said first architecture.

Claim 9

A method of expanding a data bus width of a first multiprocessor interconnection architecture having a number of data lines comprising a first bit-width and a backplane bus with a plurality of byte select lines sufficient to indicate which bytes on the data bus are active during a bus transaction cycle to create a second expanded multiprocessor interconnection architecture with an expanded bit-width and with the same plurality of byte select control lines, said method comprising the steps of: increasing the number of data lines of said first multiprocessor interconnection architecture to provide a second number of data lines in said second expanded multiprocessor interconnection architecture; providing a master request interconnection line between master and slave devices designed to utilize the expanded bit-width of the second expanded architecture, said master request line carrying a master request signal activated only by a master device designed to utilize the entire bit-width of the second expanded architecture, said master request signal indicating that the master device is attempting to initiate a transfer utilizing the entire bit-width of the second expanded architecture; providing a slave response interconnection line between master and slave devices designed to utilize the expanded bit-width of the second expanded architecture, said slave response line carrying a slave response signal activated only by a slave device designed to utilize the entire bit-width of the second expanded architecture in response to an active master request signal on said master request line, said slave response signal indicating that the slave device is designed to utilize the bit-width of the second expanded architecture; and selectively controlling the bit-width of data transferred by said master to a slave device conforming to either said first architecture or said expanded architecture in accordance with said slave response signal such that said expanded architecture does not require more byte select control lines than said first architecture.

Claim 10

A method of expanding a data bus width of a first multiprocessor interconnection architecture having a backplane data bus comprising a number of data lines with a plurality of byte select lines sufficient to indicate which bytes on the data bus are active during a bus transaction cycle, wherein expanding the backplane bus creates a second expanded multiprocessor interconnection architecture with the same plurality of byte select control lines, said method comprising the steps of: increasing said number of data lines of said first multiprocessor interconnection architecture to provide a second number of data lines in said second expanded multiprocessor interconnection architecture; providing a master request interconnection line between master and slave devices designed to utilize the second expanded architecture, said master request line carrying a master request signal activated only by a master device designed to utilize the second expanded architecture, said master request signal indicating that the master device is attempting to initiate a transfer utilizing the second expanded architecture; providing a slave response interconnection line between master and slave devices designed to utilize the second expanded architecture, said slave response line carrying a slave response signal activated only by a slave device designed to utilize the second expanded architecture in response to an active master request signal on said master request line, said slave response signal indicating that the sleeve device is designed to utilize the second expanded architecture; and selectively controlling the bit-width of data transferred by said master to a slave device conforming to either said first architecture or said expanded architecture in accordance with said slave response signal such that said expanded architecture does not require more byte select control lines than said first architecture.

Claim 11

A method of expanding a data bus width of a first multiprocessor interconnection architecture having a backplane data bus comprising a number of data lines with a plurality of byte select lines sufficient to indicate which bytes on the data bus are active during a bus transaction cycle, wherein expanding the backplane bus creates a second expanded multiprocessor interconnection architecture with the same plurality of byte select control lines, said method comprising the steps of: increasing said number of data lines of said first multiprocessor interconnection architecture to provide a second number of data lines in said second expanded multiprocessor interconnection architecture; providing a master request interconnection line between master and slave devices designed to utilize the second expanded architecture, said master request line carrying a master request signal activated only by a master device designed to utilize the second expanded architecture, said master request signal indicating that the master device is attempting to initiate a transfer utilizing the second expanded architecture; providing a slave response interconnection line between master and slave devices designed to utilize the second expanded architecture, said slave response line carrying a slave response signal activated only by a slave device designed to utilize the second expanded architecture in response to an active master request signal on said master request line, said slave response signal indicating that the sleeve device is designed to utilize the second expanded architecture; and selectively controlling the bit-width of data transferred by said master to a slave device conforming to either said first architecture or said expanded architecture in accordance with said slave response signal such that said expanded architecture does not require more byte select control lines than said first architecture.