Multi-processor data communication bus structure

Claim 2

A data communications system for transferring logically related pieces of information between the local buses connected to each of a plurality of independently operated processors and a resource, comprising: a data bus interconnecting the local buses of said processors and said resource, said data bus being capable of carrying in parallel a number of bytes each having bit length corresponding to that of the natural transfer mechanism of said processors; reading latch means associated with each processor and connected between the processors' local bus and said data bus for storing all of the bytes being simultaneously transferred over said data bus; and control logic means including, means operable during a first part of a read from the data bus by a processor to cause the latch means for said processor to latch up all simultaneously transferred bytes from said data bus while allowing one of said simultaneously transferred bytes to go to the local bus connected to said latch means, and means operable during a subsequent part of a read to transfer latched data of another of said simultaneously transferred bytes to said local bus.

Claim 3

A data communications system for transferring logically related pieces of information between the local buses connected to each of a plurality of independently operated processors and a resource, comprising: a data bus interconnecting the local buses of said processors and said resource, said data bus being capable of carrying in parallel a number of bytes each having a bit length corresponding to that of the natural transfer mechanism of said processors; writing latch means associated with each processor and connected between the processor's local bus and said data bus for storing all of the bytes to be transferred simultaneously from the local bus over said data bus; control latch means associated with each processor and having bus control signal outputs connected to the resource to which writing is required and local bus connections receiving control data from said local bus; and control logic means in said system operable during a write to the data bus by a processor to cause the writing latch means for said processor to sequentially latch up from said local bus all bytes to be transferred during said write for simultaneous transfer over said data bus during the period when the last of said sequentially latch bytes is being transferred from said local bus.

Claim 4

A data communications system for transferring logically related pieces of information between the local buses connected to each of a plurality of independently operated processors and a resource, comprising: a data bus interconnecting the local buses of said processors and said resource, said data bus being capable of carrying in parallel a number of bytes each having a bit length corresponding to that of the natural transfer mechanism of said processors; writing latch means associated with each processor and connected between the processor's local bus and said data bus for storing all of the bytes to be transferred simultaneously from the local bus over said data bus; control latch means associated with each processor and having bus control signal outputs connected to the resource to which writing is required and local bus connections receiving control data from said local bus; and control logic means in said system operable during a write to the data bus by a processor to cause the writing latch means for said processor to sequentially latch up from said local bus all bytes to be transferred during said write for simultaneous transfer over said data bus during the period when the last of said sequentially latch bytes is being transferred from said local bus.

Claim 5

A data communications system for transferring logically related pieces of information between the local buses connected to each of a plurality of independently operated processors and a resource, comprising: a data bus interconnecting the local buses of said processors and said resource, said data bus being capable of carrying simultaneously in parallel a number of bytes which have a bit length corresponding to that of the natural transfer mechanism of said processors, reading latch means associated with each processor and connected between the processors' local bus and the data bus for storing all of the bytes simultaneously transferred over said data bus, writing latch means used with each processor and connected between the processors' local bus and said data bus for sequentially storing all of the bytes from the local bus to be simultaneously transferred over said data bus, control latch means associated with each processor so as to provide bus control signal outputs to said resource when writing to said resource is to be accomplished and also to be provided with local bus connections for receiving control data from said local bus for control of the reading operation in said resource, and control logic means connected to said reading latch means, said writing latch means and said control latch means including, first means operable during a first part of a read from the data bus by a processor to cause said reading latch means for such processor to latch up all simultaneously transferred bytes from said data bus while allowing one of the simultaneously transferred bytes to go to the processor which is reading; second means operable during subsequent parts of a read from the data bus to transfer the latched data of another of said simultaneously transferred bytes from said local bus to said reading processor, and third means operable during a write to the data bus by the processor to cause the writing latch means for said processor to latch up all bytes sequentially supplied from the local bus of said processor so that all said bytes may be simultaneously transferred over said data bus during the period of transfer of the last byte from said local bus.

Claim 6

A data communications system for transferring logically related pieces of information between the local buses connected to each of a plurality of independently operated processors and a resource, comprising: a data bus interconnecting the local buses of said processors and said resource, said data bus being capable of carrying simultaneously in parallel a number of bytes which have a bit length corresponding to that of the natural transfer mechanism of said processors, reading latch means associated with each processor and connected between the processors' local bus and the data bus for storing all of the bytes simultaneously transferred over said data bus, writing latch means used with each processor and connected between the processors' local bus and said data bus for sequentially storing all of the bytes from the local bus to be simultaneously transferred over said data bus, control latch means associated with each processor so as to provide bus control signal outputs to said resource when writing to said resource is to be accomplished and also to be provided with local bus connections for receiving control data from said local bus for control of the reading operation in said resource, and control logic means connected to said reading latch means, said writing latch means and said control latch means including, first means operable during a first part of a read from the data bus by a processor to cause said reading latch means for such processor to latch up all simultaneously transferred bytes from said data bus while allowing one of the simultaneously transferred bytes to go to the processor which is reading; second means operable during subsequent parts of a read from the data bus to transfer the latched data of another of said simultaneously transferred bytes from said local bus to said reading processor, and third means operable during a write to the data bus by the processor to cause the writing latch means for said processor to latch up all bytes sequentially supplied from the local bus of said processor so that all said bytes may be simultaneously transferred over said data bus during the period of transfer of the last byte from said local bus.