Programmable data path width in a programmable unit having plural levels of subinstruction sets

Claim 1

A processing system including an arithmetic logic unit having various functional units, said system comprising: a first level subinstruction storage means; a second level subinstruction storage means; and a control register; said first level subinstruction storage means containing sequences of first level subinstructions some of which include an address to said second level subinstruction storage means, said sequences also including other first level subinstructions which contain control signals; said second level subinstruction storage means containing second level subinstructions having control signals contained therein; said control register being coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive control signals from one or the other of said storage means according to certain selected bits in a current first level subinstruction, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic unit; said arithmetic logic unit also including data buses, all of which are n bits wide, said arithmetic logic unit further including means to select n bits of said data buses for use, or m bits of said data buses for use where m is less than n, said selected means being coupled to said control register to receive information as to whether m or n bits of said data buses are to be used.