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US5296759A
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Diagonal wiring between abutting logic cells in a configurable logic array
Assignee: Atmel Corp
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Filing: 1993-06-18
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Granted: 1994-03-22
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Expires: 2013-06-18
Abstract
Abstract The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. Adjacent abutting cells logic cells are interconnectable via horizontal and vertical configurable interconnections running between adjacent cells. Furthermore, configurable diagonal interconnections run between diagonally adjacent abutting logic cells in the array.
Inventors
- 👤 Jim Sutherland
- 👤 Sanjay Popli
- 👤 Venkata Alturi
- 👤 Frederick Furtek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K17/00; H03K17/22; H03K17/223; H03K19/003; H03K19/00346; H03K19/00361; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
70 words
In a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells, adjacent abutting logic cells being interconnectable via horizontal and vertical configurable interconnections running between adjacent logic cells, the improvement comprising configurable diagonal interconnections running between diagonally adjacent abutting logic cells in the array.
Claim 2
Dependent Claim
70 words
In a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells, adjacent abutting logic cells being interconnectable via horizontal and vertical configurable interconnections running between adjacent logic cells, the improvement comprising configurable diagonal interconnections running between diagonally adjacent abutting logic cells in the array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-21 | 1997-09-20 | 1998-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-21 | 2001-09-20 | 2002-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-21 | 2005-09-20 | 2006-03-22 | $7700.00 | Window Closed / Lapsed |