Test detector/shutoff and method for BiCMOS integrated circuit

Claim 2

A test detect and shut off circuit for facilitating testing of a BiCMOS integrated circuit having a single first power rail supplying operating circuit voltage V DD and a second power rail supplying intermediate voltage V TT (wherein under normal integrated circuit operation V DD >V TT ), said BiCMOS integrated circuit including a logic portion connected between the first power rail supplying voltage V DD and a ground voltage GND, and a bipolar transistor circuit having multiple current pathways, at least one of said current pathways being connected in parallel with the logic portion between the first power rail supplying voltage V DD and the ground voltage GND, and at least one of said current pathways being connected between the first power rail supplying voltage V DD and the second power rail supplying intermediate voltage V TT , said test detect and shut off circuitry comprising: a detect circuit electrically coupled to said BiCMOS integrated circuit for detecting the presence of a predetermined test condition in said BiCMOS integrated circuit and for generating in response thereto a test detect signal; and a shut off circuit electrically coupled to said BiCMOS integrated circuit and to said detect circuit for opening the at least one bipolar transistor circuit current pathway connected between the first power rail supplying voltage V DD and ground voltage GND in response to generation of said test detect signal by said detect circuit such that bias current in said at least one bipolar transistor circuit current pathway is eliminated, thereby facilitating testing of the logic portion of said BiCMOS integrated circuit.

Claim 3

The test detect and shut off circuit of claim 1, wherein said test to be facilitated comprises IDD testing of the logic portion of said BiCMOS integrated circuit.

Claim 4

The test detect and shut off circuit of claim 2, wherein said predetermined test condition comprises approximately equal voltage levels being supplied by said first power rail and said second power rail.

Claim 5

The test detect and shut off circuit of claim 2, wherein said predetermined test condition comprises a predefined minimum voltage difference between said supplied voltage V DD and said supplied voltage V TT .

Claim 6

The test detect and shut off circuit of claim 1, wherein said shut off circuit comprises at least one field effect transistor connected in series with said at least one bipolar transistor circuit current pathway in parallel with said logic portion between said first power rail supplying voltage V DD and said ground voltage GND, said at least one field effect transistor being coupled to receive said test detect signal generated by said detect circuit and function as a pass gate.

Claim 7

A BiCMOS integrated circuit having a test detect and bipolar circuit shutoff for facilitating IDD testing of a logic portion of said BiCMOS integrated circuit, said BiCMOS integrated circuit comprising: a single first power input for supplying operating circuit voltage V DD to said BiCMOS integrated circuit; a field effect transistor circuit connected between said first power input supplying voltage V DD and a ground voltage GND, said field effect transistor circuit comprising said logic portion of said BiCMOS integrated circuit; a bipolar transistor circuit having a first circuit portion comprising multiple current pathways connected in parallel with said field effect transistor circuit between said first power input supplying voltage V DD and said ground voltage GND; a second power input for supplying an intermediate circuit voltage V TT (wherein under normal integrated circuit operation V DD >V TT >GND) to a second circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V DD and said second power input supplying voltage V TT ; and detect/shutoff circuitry coupled to said bipolar transistor circuit for detecting the presence of a predetermined test condition in said BiCMOS integrated circuit, and upon detection of said predetermined test condition for switching off said current pathways of said first circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V DD and said ground voltage GND such that quiescent current in said current pathways of said first circuit portion is eliminated, thereby facilitating IDD testing of said logic portion of said BiCMOS integrated circuit.

Claim 8

A BiCMOS integrated circuit having a test detect and bipolar circuit shutoff for facilitating IDD testing of a logic portion of said BiCMOS integrated circuit, said BiCMOS integrated circuit comprising: a single first power input for supplying operating circuit voltage V DD to said BiCMOS integrated circuit; a field effect transistor circuit connected between said first power input supplying voltage V DD and a ground voltage GND, said field effect transistor circuit comprising said logic portion of said BiCMOS integrated circuit; a bipolar transistor circuit having a first circuit portion comprising multiple current pathways connected in parallel with said field effect transistor circuit between said first power input supplying voltage V DD and said ground voltage GND; a second power input for supplying an intermediate circuit voltage V TT (wherein under normal integrated circuit operation V DD >V TT >GND) to a second circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V DD and said second power input supplying voltage V TT ; and detect/shutoff circuitry coupled to said bipolar transistor circuit for detecting the presence of a predetermined test condition in said BiCMOS integrated circuit, and upon detection of said predetermined test condition for switching off said current pathways of said first circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V DD and said ground voltage GND such that quiescent current in said current pathways of said first circuit portion is eliminated, thereby facilitating IDD testing of said logic portion of said BiCMOS integrated circuit.

Claim 9

The BiCMOS integrated circuit of claim 6, wherein said predetermined test condition comprises approximately equal voltage values being supplied at said single first power input (V DD ) and said second power input (V TT ), and wherein said BiCMOS integrated circuit further includes means for approximately equalizing the voltage values supplied at said first power input and said second power input.

Claim 10

The BiCMOS integrated circuit of claim 7, wherein said means for approximately equalizing voltage V DD and voltage V TT comprises means for raising voltage value V TT at said second power input to substantially equal said voltage value V DD supplied at said single first power input.

Claim 11

The BiCMOS integrated circuit of claim 8, wherein said predetermined test condition comprises a predefined minimum voltage difference between said supplied voltage V DD and said supplied voltage V TT .

Claim 12

The BiCMOS integrated circuit of claim 6, wherein said detect/shutoff circuitry for switching off said first circuit portion pathways of said bipolar transistor circuit connected between said first power input supplying voltage V DD and said ground voltage GND includes for each current pathway of said first circuit portion pathways a field effect transistor connected in series therewith so as to function as a pass gate.

Claim 13

The BiCMOS integrated circuit of claim 6, wherein said field effect transistor circuit comprises a CMOS logic circuit connected between said single first power input supplying voltage V DD and said ground voltage GND.

Claim 14

The BiCMOS integrated circuit of claim 6, wherein an operating circuit voltage V DD supplied by said first power input comprises 3.6 volts and an operating circuit voltage V TT supplied by said second power input comprises 1.5 volts.

Claim 17

The testing method of claim 13, wherein said reducing step (a) comprises raising the voltage level of said intermediate supply voltage V TT to approximately equal said operating supply voltage V DD .