US5019772A — Test selection techniques

Claim 1

Independent Claim 114 words

An integrated circuit system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin and disposed on said semiconductor substrate and operable at a first voltage, test selection means having an output terminal connected to said pin for producing a control pulse at said output terminal for a given period of time and operable at a second voltage higher than said first voltage, means for applying said second voltage to said pin during a first portion of said given period of time, and means for applying said first voltage to said pin during a second portion of said given period of time without said first portion.

Claim 2

Dependent Claim 114 words

An integrated circuit system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin and disposed on said semiconductor substrate and operable at a first voltage, test selection means having an output terminal connected to said pin for producing a control pulse at said output terminal for a given period of time and operable at a second voltage higher than said first voltage, means for applying said second voltage to said pin during a first portion of said given period of time, and means for applying said first voltage to said pin during a second portion of said given period of time without said first portion.

Claim 3

Dependent Claim 18 words

An integrated circuit system as set forth in claim 1 wherein said test selection means includes a latch.

Claim 4

Dependent Claim 39 words

An integrated circuit system as set forth in claim 2 wherein said test selection means comprises a series circuit including a series of diodes in series with a resistor connected between said pin and a point of reference potential.

Claim 5

Dependent Claim 25 words

An integrated circuit system as set forth in claim 3 wherein said series circuit includes isolating means for interrupting current flow through said series circuit.

Claim 6

Dependent Claim 22 words

An integrated circuit system as set forth in claim 4 wherein said isolating means includes a transistor responsive to said first voltage.

Claim 7

Dependent Claim 201 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a first control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit means having an output connected to the input of said latch and an input responsive to the first control voltage from the output of said control voltage circuit means for producing a second control voltage at the output of said latch conditioning circuit means during said first period of time, means for initially applying a supply source voltage to said latch after producing said second control voltage, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time without said first period of time.

Claim 8

Dependent Claim 201 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a first control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit means having an output connected to the input of said latch and an input responsive to the first control voltage from the output of said control voltage circuit means for producing a second control voltage at the output of said latch conditioning circuit means during said first period of time, means for initially applying a supply source voltage to said latch after producing said second control voltage, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time without said first period of time.

Claim 9

Dependent Claim 23 words

A test selection system as set forth in claim 6 wherein said control voltage circuit means includes a plurality of serially arranged diodes.

Claim 10

Dependent Claim 34 words

A test selection system as set forth in claim 7 wherein said control voltage circuit means further includes a resistor connected between said plurality of serially arranged diodes and a point of reference potential.

Claim 11

Dependent Claim 31 words

A test selection system as set forth in claim 8 wherein said control voltage circuit means further includes an isolating device interposed between said pin and said point of reference potential.

Claim 12

Dependent Claim 57 words

A test selection system as set forth in claim 6 wherein said latch includes first and second inverters each having an input and an output with the output of said first inverter being connected to the input of said second inverter and the output of the second inverter being connected to the input of said first inverter.

Claim 13

Dependent Claim 27 words

A test selection system as set forth in claim 10 wherein each of said inverters includes a P-channel field effect transistor and an N-channel field effect transistor.

Claim 14

Dependent Claim 21 words

A test selection system as set forth in claim 6 further including a capacitor connected to the output of said latch.

Claim 15

Dependent Claim 54 words

A test selection system as set forth in claim 6 further including a logic circuit having first and second inputs and an output, the first input of said logic circuit being connected to said test enable terminal and the second input of said logic circuit being connected to a source of address input signals.

Claim 16

Dependent Claim 18 words

A test selection system as set forth in claim 13 wherein said logic circuit is an AND circuit.

Claim 17

Dependent Claim 50 words

A test selection system as set forth in claim 14 wherein said AND circuit comprises a NAND circuit including the first and second inputs of said logic circuit and an inverter, with said inverter being interposed between the output of said NAND circuit and the output of said logic circuit.

Claim 18

Dependent Claim 39 words

A test selection system as set forth in claim 6 further including a second pin connected to said semiconductor substrate, and a disabling circuit connected to said second pin and having an output coupled to said latch conditioning circuit.

Claim 19

Dependent Claim 35 words

A test selection system as set forth in claim 16 wherein said disabling circuit includes a plurality of serially arranged diodes and a resistor connected between said second pin and a point of reference potential.

Claim 20

Dependent Claim 148 words

An integrated circuit system comprising a semiconductor substrate, first and second pins connected to said semiconductor substrate, integrated circuit means connected to said first and second pins and disposed on said semiconductor substrate operable at a first operating voltage during first and second periods of time, first control voltage circuit means connected to said first pin for producing a first control voltage and operable at a second operating voltage having a magnitude larger than that of said first operating voltage, latching means responsive to said first control voltage for establishing said latching means in a first state during said first period of time, and second control voltage circuit means operable at said second operating voltage and connected to said second pin producing a second control voltage for establishing said latching means in a second state during said second period of time subsequent to said first period of time.

Claim 21

Dependent Claim 148 words

An integrated circuit system comprising a semiconductor substrate, first and second pins connected to said semiconductor substrate, integrated circuit means connected to said first and second pins and disposed on said semiconductor substrate operable at a first operating voltage during first and second periods of time, first control voltage circuit means connected to said first pin for producing a first control voltage and operable at a second operating voltage having a magnitude larger than that of said first operating voltage, latching means responsive to said first control voltage for establishing said latching means in a first state during said first period of time, and second control voltage circuit means operable at said second operating voltage and connected to said second pin producing a second control voltage for establishing said latching means in a second state during said second period of time subsequent to said first period of time.

Claim 22

Dependent Claim 47 words

An integrated circuit system as set forth in claim 18 wherein each of said first and second control voltage circuit means includes a series circuit having a plurality of diodes and a resistor connected between said first and second pins, respectively, and a point of reference potential.

Claim 23

Dependent Claim 209 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, said control voltage circuit means including a plurality of serially arranged diodes, a resistor connected between said plurality of serially arranged diodes and a point of reference potential and an isolating device interposed between said pin and said point of reference potential, means for activating said isolating device after said control voltage is produced, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 24

Dependent Claim 209 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, said control voltage circuit means including a plurality of serially arranged diodes, a resistor connected between said plurality of serially arranged diodes and a point of reference potential and an isolating device interposed between said pin and said point of reference potential, means for activating said isolating device after said control voltage is produced, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 25

Dependent Claim 191 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, said latch conditioning circuit including first and second serially connected transistors having its output at the common point between said transistors and its input at a control electrode of one of said first and second transistors, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 26

Dependent Claim 191 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, said latch conditioning circuit including first and second serially connected transistors having its output at the common point between said transistors and its input at a control electrode of one of said first and second transistors, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 27

Dependent Claim 215 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, said buffer circuit including first and second inverters each having an input and an output, with the input of said first inverter being connected to the output of said latch and the output of said first inverter being connected to the input of said second inverter, and an output of said second inverter being connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 28

Dependent Claim 215 words

A test selection system comprising a semiconductor substrate, a pin connected to said semiconductor substrate, integrated circuit means connected to said pin operable at a first operating voltage within a given voltage range, control voltage circuit means connected to said pin having an output producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin during a first period of time, a latch having an input and an output, a latch conditioning circuit having an output connected to the input of said latch and an input responsive to the control voltage from the output of said control voltage circuit means, a test enable terminal, a buffer circuit having an input connected to the output of said latch and an output connected to said test enable terminal, said buffer circuit including first and second inverters each having an input and an output, with the input of said first inverter being connected to the output of said latch and the output of said first inverter being connected to the input of said second inverter, and an output of said second inverter being connected to said test enable terminal, and means for applying said first operating voltage to said pin during a second period of time.

Claim 29

Dependent Claim 35 words

A test selection system as set forth in claim 20 wherein said isolating means includes a transistor and said activating means includes means for applying said first voltage to a control electrode of said transistor.

Claim 30

Dependent Claim 40 words

A test selection system as set forth in claim 23 wherein said transistor is a P-channel field effect transistor and wherein each diode of said plurality of serially arranged diodes is an N-channel field effect transistor arranged as a diode.

Claim 31

Dependent Claim 91 words

A test selection system as set forth in claim 21 wherein said first transistor is a P-channel field effect transistor connected between the output of said latch conditioning circuit and a first point of reference potential and having a control electrode connected to the output of said latch conditioning circuit, and said second transistor is an N-channel field effect transistor connected between a second point of reference potential and the output of the latch conditioning circuit and having a control electrode connected to the output of said control voltage circuit means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-05-27	1994-11-26	1995-05-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-05-27	1998-11-26	1999-05-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-05-27	2002-11-26	2003-05-28	$7700.00	Window Closed / Lapsed

Test selection techniques

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