US4833395A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a test circuit
Assignee: Fujitsu Ltd
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Filing: 1987-10-23
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Granted: 1989-05-23
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Expires: 2007-10-23
Abstract
Abstract A semiconductor device comprises a test signal generating circuit for generating a test signal having an arbitrary frequency, a first buffer for selectively outputting one of the test signal and an external input signal, at least one test circuit supplied with an output signal of the first buffer, an external output terminal, a logic circuit, a second buffer for selectively supplying to the external terminal one of the test signal from the test circuit and an output signal of the logic circuit, and a switching signal generating circuit for generating switching signals for the first and second buffers. The state of the test circuit is checked by use of the test signal to indirectly determine the state of the logic circuit.
Inventors
- 👤 Takeshi Sasaki
- 👤 Hideo Monma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:59
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
275 words
A semiconductor device operating in first and second modes, said device comprising: an external input terminal for receiving an external input signal; an external output terminal; a test signal generating means for generating a test signal having an arbitrary frequency; a switching signal generating means for generating a switching signal and inputting said switching signal to said test signal generating means; a logic circuit means for processing said external input signal in said second mode; at least one test circuit means for detecting a defect of said logic circuit means indirectly, said test circuit means having a predetermined circuit structure; a first buffer means, having a first input terminal connected to said external input terminal for receiving said external input signal, a second input terminal connected to said test signal generating means for receiving said test signal, a first output terminal connected to said logic circuit means, and a second output terminal connected to said test circuit means, said first buffer means receiving said switching signal for supplying said test signal to said test circuit means in said first mode and for supplying said external input signal to said logic circuit means in said second mode, in response to said received switching signal; and a second buffer means connected to said test circuit means, said logic circuit means, and said external output terminal, said second buffer means receiving said switching signal for supplying an output of said test circuit means to said external output terminal in said first mode and for supplying an output of said logic circuit means to said external output terminal in said second mode, in response to said received switching signal.
Claim 2
Dependent Claim
275 words
A semiconductor device operating in first and second modes, said device comprising: an external input terminal for receiving an external input signal; an external output terminal; a test signal generating means for generating a test signal having an arbitrary frequency; a switching signal generating means for generating a switching signal and inputting said switching signal to said test signal generating means; a logic circuit means for processing said external input signal in said second mode; at least one test circuit means for detecting a defect of said logic circuit means indirectly, said test circuit means having a predetermined circuit structure; a first buffer means, having a first input terminal connected to said external input terminal for receiving said external input signal, a second input terminal connected to said test signal generating means for receiving said test signal, a first output terminal connected to said logic circuit means, and a second output terminal connected to said test circuit means, said first buffer means receiving said switching signal for supplying said test signal to said test circuit means in said first mode and for supplying said external input signal to said logic circuit means in said second mode, in response to said received switching signal; and a second buffer means connected to said test circuit means, said logic circuit means, and said external output terminal, said second buffer means receiving said switching signal for supplying an output of said test circuit means to said external output terminal in said first mode and for supplying an output of said logic circuit means to said external output terminal in said second mode, in response to said received switching signal.
Claim 3
Dependent Claim
23 words
A semiconductor device as claimed in claim 1 wherein said test circuit means is located in a vicinity of said logic circuit means.
Claim 4
Dependent Claim
111 words
A semiconductor device as claimed in claim 1 in which said first buffer means comprises a buffer amplifier, first gate means provided in an input stage of said buffer amplifier for selectively supplying to said buffer amplifier said test signal from said test signal generating means in said first mode and said external input signal from said external input terminal in said second mode responsive to said switching signals, and second gate means provided in an output stage of said buffer amplifier for selectively supplying an output signal of said buffer amplifier to said test circuit means in said first mode and to said logic circuit means in said second mode.
Claim 5
Dependent Claim
64 words
A semiconductor device as claimed in claim 1 in which said second buffer means comprises a buffer amplifier, and gate means provided in an input stage of said buffer amplifier for selectively supplying to said external output terminal the test signal received through said test circuit means in said first mode and the output signal of said logic circuit means in said second mode.
Claim 6
Dependent Claim
66 words
A semiconductor device as claimed in claim 1 in which said test signal generating means comprises first and second voltage controlled oscillators supplied with a control voltage, and a NAND circuit supplied with output signals of said first and second voltage controlled oscillators for producing said test signal, said first and second voltage controlled oscillators having mutually different input control voltage versus output oscillation frequency characteristics.
Claim 7
Dependent Claim
28 words
A semiconductor device as claimed in claim 5 which further comprises a voltage supply circuit for supplying said control voltage to said first and second voltage controlled oscillators.
Claim 8
Dependent Claim
28 words
A semiconductor device as claimed in claim 6 in which said voltage supply circuit supplies a variable control voltage to variably control the frequency of said test signal.
References Cited (Backward Citations)
FR2305098A1
Cited
FR2393426A1
Cited
US4465971A
Cited
WO1984002580A1
Cited
EP0141681A2
Cited
US4697140A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |