Semiconductor memory device

Abstract

Abstract PURPOSE:To facilitate the measurement of a threshold voltage in an erasing condition by impressing a voltage higher than a supply voltage selectively applied to an external input terminal directly to the control gate of a memory transistor in response to the control signal of the supply voltage level. CONSTITUTION:At the time of a test mode, transistors TR Q10 and T1 are turned on by a testing control signal T, a current flow from a high voltage generating circuit 5 to a high voltage switch 4, and a MOS capacitor C1 is changed. In this condition, a circuit 4 raise the potential of a node N2 at every rise and fall of a control clock phi, and the voltage rises near a high voltage VPP. On the other hand, a test voltage applied from an external terminal 14 is given through a TR Q9 and an erasing high voltage pulse line EL to the gate of a TR Q7. Thus, the voltage necessary for the test is applied to a control gate line CGL, and the measurement of the threshold voltage is facilitated.

Inventors

• 👤 Takeshi Nakayama
• 👤 Masanori Hayashigoe
• 👤 Kazuo Kobayashi
• 👤 Yasushi Terada
• 👤 Yoshikazu Miyawaki

Bibliographic Details